Commits · e8e7b2cb46bb16a8939567d770c3f69df35e7bdc · Roger Ferrer / llvm-epi · GitLab

May 28, 2020
- [ARM] More tests for MVE LSR and float issues. NFC · e8e7b2cb
  David Green authored May 28, 2020
  
  e8e7b2cb
- [MachineVerifier] Verify that a DBG_VALUE has a debug location · 4855534d
  Vedant Kumar authored May 27, 2020
  4855534d
- Add tests for preallocated + musttail · 06803d7a
  Arthur Eubanks authored May 28, 2020
  06803d7a
- AMDGPU/GlobalISel: precommit extractelement test. NFC. · 6c824c81
  Stanislav Mekhanoshin authored May 28, 2020
  
  6c824c81
- AMDGPU: Add intrinsic for s_setreg · 97f3f0ba
  Matt Arsenault authored May 06, 2020
  97f3f0ba
- [SDAG] Don't require LazyBlockFrequencyInfo at optnone · e0e5c644
  Nikita Popov authored May 21, 2020
  e0e5c644
- [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate · b726d071
  alex-t authored May 22, 2020
  b726d071
- [x86] Propagate memory operands during call frame optimization · f5192d7f
  Jean-Michel Gorius authored May 28, 2020
  f5192d7f
- AMDGPU: Add missing test for s_denorm_mode scheduling · 06019e31
  Matt Arsenault authored May 28, 2020
  06019e31
- [X86][SSE] Peek though MOVMSK source sign bits using SimplifyMultipleUseDemandedBits · 1ddac956
  Simon Pilgrim authored May 28, 2020
  1ddac956
- [AArch64] Precommit new fp extraction/insertion test. · ab95ac01
  Florian Hahn authored May 28, 2020
  
  ab95ac01
- [AArch64][SVE] Add support for spilling/filling ZPR2/3/4 · 8a397b66
  Cullen Rhodes authored May 28, 2020
  8a397b66
- [ARM] Improve codegen of volatile load/store of i64 · c010d4d1
  Victor Campos authored Mar 09, 2020
  c010d4d1
- AMDGPU/GlobalISel: Fixed insert element for non-standard vectors · 7392bbc3
  Stanislav Mekhanoshin authored May 27, 2020
  7392bbc3
- AMDGPU: Support non-entry block static sized allocas · 5e007fe9
  Matt Arsenault authored May 27, 2020
  5e007fe9
- AMDGPU/GlobalISel: Fixed handling of non-standard vectors · 8aa81aae
  Stanislav Mekhanoshin authored May 21, 2020
  8aa81aae
May 27, 2020
- Enable `align <n>` to be used in the intrinsic definition. · fa342b5c
  Michael Liao authored May 27, 2020
  fa342b5c
- [TargetPassConfig] Add CanonicalizeFreezeInLoops before LSR · 54b64572
  Juneyoung Lee authored May 28, 2020
  54b64572
- [GlobalISel] Don't combine instructions which are fed by memory instructions. · c593bf53
  Jessica Paquette authored May 15, 2020
  c593bf53
- [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO. · eb1092ad
  alex-t authored May 18, 2020
  eb1092ad
- [X86] Restore selection of MULX on BMI2 targets. · 8e7e6a8d
  Craig Topper authored May 27, 2020
  8e7e6a8d
- AMDGPU: Start adding MODE register uses to instructions · 4b449631
  Matt Arsenault authored May 27, 2020
  4b449631
- [BPF] simplify zero extension with MOV_32_64 · 13f6c81c
  John Fastabend authored May 27, 2020
  13f6c81c
- [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm · 2368bf52
  Lei Huang authored May 27, 2020
  2368bf52
- AMDGPU: Fix dropping MI flags when rewriting instructions · 07cd19ef
  Matt Arsenault authored May 26, 2020
  07cd19ef
- Start migrating away from statepoint's inline length prefixed argument bundles · 1af3705c
  Philip Reames authored May 27, 2020
  1af3705c
- Revert "[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm" · 559845f8
  Lei Huang authored May 27, 2020
  559845f8
- [AArch64][BFloat] add BFloat instruction support for AArch64 · 78bd0c0e
  Ties Stuij authored May 27, 2020
  78bd0c0e
- AMDGPU: Fix backwards s_cselect_* operands · 833996ce
  Matt Arsenault authored May 19, 2020
  833996ce
- [ARM] Fix rewrite of frame index in Thumb2's address mode i8s4 · c7593b0f
  Victor Campos authored May 26, 2020
  c7593b0f
- [X86][SSE] Convert PTEST to MOVMSK for allsign bits vector results · 410667f1
  Simon Pilgrim authored May 27, 2020
  410667f1
- [GlobalISel][InlineAsm] Add missing EarlyClobber flag to inline asm output operands · f2fad3f7
  Konstantin Schwarz authored May 23, 2020
  f2fad3f7
- [VE] Dynamic stack allocation · dedaf3a2
  Kazushi (Jam) Marukawa authored May 27, 2020
  dedaf3a2
- [NFC][PowerPC] Modify the test case two-address-crash.mir · 23a2f452
  Kang Zhang authored May 27, 2020
  
  23a2f452
- GlobalISel: Basic legalization for G_PTRMASK · ef3e8312
  Matt Arsenault authored May 23, 2020
  
  ef3e8312
- [AArch64][GlobalISel] Do not modify predicate when optimizing G_ICMP · ae597a77
  Jessica Paquette authored May 26, 2020
  ae597a77
May 26, 2020
- [AMDGPU] Bail alloca vectorization if GEP not found · 512e806a
  Stanislav Mekhanoshin authored May 26, 2020
  512e806a
- AMDGPU: Fix wrong null value for private address space · bb10fa3a
  Matt Arsenault authored May 24, 2020
  bb10fa3a
- [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm · 7eb666b1
  Lei Huang authored May 15, 2020
  7eb666b1
- [PowerPC][NFC] Update test to prevent DCE from causing failures · 6e9223a2
  Nemanja Ivanovic authored May 26, 2020
  6e9223a2