Commits · e9a2f4fe2cac1b37a0370599c800e3f50fdd82f3 · Roger Ferrer / llvm-epi · GitLab

Jun 27, 2019
- [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2) · 0627b098
  Roman Lebedev authored Jun 27, 2019
  0627b098
- [LiveDebugValues] Emit the debug entry values · d6a46aff
  Djordje Todorovic authored Jun 27, 2019
  d6a46aff
- [LiveRangeEdit] Fix build failure caused by the rL364536 · 7a9ca67f
  Djordje Todorovic authored Jun 27, 2019
  7a9ca67f
- [TargetLowering] SimplifyDemandedVectorElts - add shift/rotate support. · 83e1a1e7
  Simon Pilgrim authored Jun 27, 2019
  83e1a1e7
- [DWARF] Handle the DW_OP_entry_value operand · a0d45058
  Djordje Todorovic authored Jun 27, 2019
  a0d45058
- [TargetLowering] SimplifyDemandedBits - use DemandedElts to better identify... · c692a8dc
  Simon Pilgrim authored Jun 27, 2019
  c692a8dc
- [Backend] Keep call site info valid through the backend · 71d3869f
  Djordje Todorovic authored Jun 27, 2019
  71d3869f
- [ISEL][X86] Tracking of registers that forward call arguments · 7eeeb594
  Djordje Todorovic authored Jun 27, 2019
  7eeeb594
- [DebugInfo] Avoid register coalesing unsoundly changing DBG_VALUE locations · d528bcd9
  Jeremy Morse authored Jun 27, 2019
  d528bcd9
- [GlobalISel] Remove [un]packRegs from IRTranslator · 74a50a72
  Diana Picus authored Jun 27, 2019
  74a50a72
- [GlobalISel] Accept multiple vregs for lowerCall's args · 43fb5ae5
  Diana Picus authored Jun 27, 2019
  43fb5ae5
- [GlobalISel] Accept multiple vregs for lowerCall's result · 81389961
  Diana Picus authored Jun 27, 2019
  81389961
- [GlobalISel] Accept multiple vregs in lowerFormalArgs · c3dbe239
  Diana Picus authored Jun 27, 2019
  c3dbe239
- [GlobalISel] Allow multiple VRegs in ArgInfo. NFC · 69ce1c13
  Diana Picus authored Jun 27, 2019
  69ce1c13
- [MachineFunction] Base support for call site info tracking · a7cde103
  Djordje Todorovic authored Jun 27, 2019
  a7cde103
- [IR] Add DISuprogram and DIE for a func decl · 59b39faa
  Djordje Todorovic authored Jun 27, 2019
  59b39faa
Jun 26, 2019
- PEI: Add default handling of spills to registers · 47345534
  Matt Arsenault authored Jun 26, 2019
  47345534
- [CodeGen] Improve formatting of jump tables (NFC) · 42e13c83
  Evandro Menezes authored Jun 26, 2019
  42e13c83
- [X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness · b0ecc1cc
  Roman Lebedev authored Jun 26, 2019
  b0ecc1cc
- Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline." · 2851248f
  Clement Courbet authored Jun 26, 2019
  2851248f
- [HardwareLoops] NFC - move loop with irreducible control flow checking logic to HarewareLoopInfo. · aa999528
  Chen Zheng authored Jun 26, 2019
  aa999528
- [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline. · 7b3a5f0e
  Clement Courbet authored Jun 26, 2019
  7b3a5f0e
- [DAGCombine] visitEXTRACT_SUBVECTOR - add TODO for extract_subvector(bitcast()) support · a6319e5f
  Simon Pilgrim authored Jun 26, 2019
  a6319e5f
- [HardwareLoops] NFC - move loop with irreducible control flow checking logic... · 46ce9e4f
  Chen Zheng authored Jun 26, 2019
  46ce9e4f
- Teach the DAGCombine to fold this pattern(c1 and c2 is constant). · e0e7d4c3
  QingShan Zhang authored Jun 26, 2019
  e0e7d4c3
Jun 25, 2019
- [MachinePipeliner] Fix risky iterator usage R++, --R · fee855b5
  Jinsong Ji authored Jun 25, 2019
  fee855b5
- [Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr) · be0dedb2
  Philip Reames authored Jun 25, 2019
  be0dedb2
- [DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal · 9762b260
  Simon Pilgrim authored Jun 25, 2019
  9762b260
- [SDAG] expand ctpop != 1 · 685c5cbc
  Sanjay Patel authored Jun 25, 2019
  685c5cbc
- [TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support · 1a18bb6f
  Simon Pilgrim authored Jun 25, 2019
  1a18bb6f
- [TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG · 36953ce7
  Simon Pilgrim authored Jun 25, 2019
  36953ce7
- [SDAG] improve expansion of ctpop+setcc · e4ef6229
  Sanjay Patel authored Jun 25, 2019
  e4ef6229
- [TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG · 69fc1111
  Simon Pilgrim authored Jun 25, 2019
  69fc1111
- [VectorLegalizer] ExpandANY_EXTEND_VECTOR_INREG/ExpandZERO_EXTEND_VECTOR_INREG... · b23c942c
  Simon Pilgrim authored Jun 25, 2019
  b23c942c
- [TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND · 49b3778e
  Simon Pilgrim authored Jun 25, 2019
  49b3778e
- [Codegen] TargetLowering::SimplifySetCC(): omit urem when possible · cdd43eac
  Roman Lebedev authored Jun 25, 2019
  cdd43eac
- [ExpandMemCmp] Move all options to TargetTransformInfo. · 3bc5ad55
  Clement Courbet authored Jun 25, 2019
  3bc5ad55
- Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..." · 079924b0
  Craig Topper authored Jun 25, 2019
  079924b0
Jun 24, 2019
- [CodeGen] Add missing vector type legalization for ctlz_zero_undef · ea08248b
  Roland Froese authored Jun 24, 2019
  ea08248b
- GlobalISel: Remove unsigned variant of SrcOp · faeaedf8
  Matt Arsenault authored Jun 24, 2019
  faeaedf8