Commits · ea8ca34e3a5b3c8246af93617be3fdc1abcf4a3c · Roger Ferrer / llvm-epi · GitLab

May 30, 2011
- Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are · ea8ca34e
  Rafael Espindola authored May 30, 2011
  ea8ca34e
- Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece · 595fd7a0
  Rafael Espindola authored May 30, 2011
  595fd7a0
May 29, 2011
- On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. · 7d84ece0
  John McCall authored May 29, 2011
  7d84ece0
- I didn't mean to commit these residues of a personal project. · e64371b9
  John McCall authored May 29, 2011
  e64371b9
- On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. · 085d891d
  John McCall authored May 29, 2011
  085d891d
- Fix to match the dwarf register numbers that gdb uses. · 0f17990f
  Rafael Espindola authored May 29, 2011
  0f17990f
- Dwarf register 0 is r0, remove incorrect entries. · ccfd392c
  Rafael Espindola authored May 29, 2011
  ccfd392c
- Remove the dwarf numbers from the D registers. They don't have dwarf numbers · fd75d45b
  Rafael Espindola authored May 29, 2011
  fd75d45b
May 28, 2011
- Fix ARM fast isel to correctly flag memory operands to stores. This fixes · 6528a549
  Cameron Zwarich authored May 28, 2011
  6528a549
- Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs · 325110f3
  Bruno Cardoso Lopes authored May 28, 2011
  325110f3
- This actually starts at offset 0, not 1. · 368976f5
  Eric Christopher authored May 28, 2011
  368976f5
- Change the set of callee-saved registers for non-MIPS32 architectures specified · a6664cdb
  Akira Hatanaka authored May 28, 2011
  a6664cdb
- Implement the 'M' output modifier for arm inline asm. This is fairly · d00e8ad8
  Eric Christopher authored May 28, 2011
  d00e8ad8
- Define a wrapper node for target constant nodes (tglobaladdr, etc.). · b406843f
  Akira Hatanaka authored May 28, 2011
  b406843f
- Add 132187 back now that the real problem is fixed. · 19fea7a8
  Rafael Espindola authored May 28, 2011
  19fea7a8
- Fix the remaining atomic intrinsics to use the right register classes on Thumb2, · 1d553a2c
  Cameron Zwarich authored May 27, 2011
  1d553a2c
- ARM asm parser wasn't able to parse a "mov" instruction while in Thumb · 787dfadc
  Bruno Cardoso Lopes authored May 27, 2011
  787dfadc
- It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check. · a5149b5c
  Rafael Espindola authored May 27, 2011
  a5149b5c
- Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass() · 75d99e4b
  Cameron Zwarich authored May 27, 2011
  75d99e4b
- Make size computation less brittle. · d23bfb8a
  Rafael Espindola authored May 27, 2011
  d23bfb8a
May 27, 2011
- Don't use movw / movt for iOS static codegen for now to workaround some tools... · 518bcd0e
  Evan Cheng authored May 27, 2011
  518bcd0e
- Delete MethodBodies that only filtered reserved registers. · 60199449
  Jakob Stoklund Olesen authored May 27, 2011
  60199449
- Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 · fe84bd65
  Eli Friedman authored May 27, 2011
  fe84bd65
- Remove DwarfRegNum from the individual bits of the condition register. · 0373d007
  Rafael Espindola authored May 27, 2011
  0373d007
- Remove DwarfRegNum from CARRY. I should be encoded with DW_OP_bit_piece. · ecb55730
  Rafael Espindola authored May 27, 2011
  ecb55730
- Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to · 2daba338
  Rafael Espindola authored May 27, 2011
  2daba338
- Make the branch encoding for tBcc more obvious that it's a 4-byte opcode · 9b67db8e
  Eric Christopher authored May 27, 2011
  9b67db8e
- Fix comment. · bd59e893
  Eric Christopher authored May 27, 2011
  bd59e893
- Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. · b362884c
  Chad Rosier authored May 26, 2011
  b362884c
May 26, 2011
- Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if · 077964a0
  Akira Hatanaka authored May 26, 2011
  077964a0
- Fix some dwarf register numbers. · e3a07a3b
  Rafael Espindola authored May 26, 2011
  e3a07a3b
- Add support for C++ exception handling. · aa560006
  Akira Hatanaka authored May 26, 2011
  aa560006
- Reorganize these slightly according to operand type. · 33a73c77
  Eric Christopher authored May 26, 2011
  33a73c77
- Set HasSetDirective to true. · 8062bf36
  Akira Hatanaka authored May 26, 2011
  8062bf36
- Reverting 132105: it broke some LLVM-GCC DejaGNU tests. · 493a12bf
  Stuart Hastings authored May 26, 2011
  493a12bf
- Mark tBX as an indirect branch rather than a return. · 26ddb121
  Cameron Zwarich authored May 26, 2011
  26ddb121
- Correctly handle a one-word struct passed byval on x86_64. · 276f231c
  Stuart Hastings authored May 26, 2011
  276f231c
- Rewrite fast-isel integer cast handling to handle more cases, and to be... · c7035519
  Eli Friedman authored May 25, 2011
  c7035519
- Define WeakRefDirective. · fa63d309
  Akira Hatanaka authored May 25, 2011
  fa63d309
May 25, 2011
- Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. · a946f476
  Cameron Zwarich authored May 25, 2011
  a946f476