Commits · eb31c3c5cbedf3fc74b9db73419847b14cbe45e6 · Roger Ferrer / llvm-epi · GitLab

Feb 09, 2021
- AMDGPU: Fix verifier error with argument passed in CSR SGPR · f4ca6d82
  Matt Arsenault authored Feb 04, 2021
  f4ca6d82
- GlobalISel: Fix using wrong calling convention for callees · b72a2365
  Matt Arsenault authored Feb 08, 2021
  b72a2365
- Revert "[CostModel] Remove VF from IntrinsicCostAttributes" · 92028062
  Jinsong Ji authored Feb 09, 2021
  92028062
Feb 08, 2021
- AMDGPU: Stop adding stack passed wide arguments to call conv handler · bcf723b2
  Matt Arsenault authored Feb 07, 2021
  bcf723b2
- [AMDGPU] Use named unified buffer format constant. NFC. · a4b1df8a
  Jay Foad authored Feb 08, 2021
  
  a4b1df8a
- [AMDGPU]: Fixes an invalid clamp selection pattern. · f89f6d1e
  Thomas Symalla authored Feb 02, 2021
  f89f6d1e
- [AMDGPU][MC] Corrected error position for invalid dim modifiers · 05433a8d
  Dmitry Preobrazhensky authored Feb 08, 2021
  05433a8d
- [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands · 168ccc8e
  Dmitry Preobrazhensky authored Feb 08, 2021
  168ccc8e
Feb 06, 2021
- [AMDGPU] Drop unnecessary const from a return type (NFC) · 7725b818
  Kazu Hirata authored Feb 05, 2021
  7725b818
Feb 05, 2021
- [NFC] Simplify expression · 79b3ab72
  Guillaume Chatelet authored Feb 05, 2021
  
  79b3ab72
- [CostModel] Remove VF from IntrinsicCostAttributes · 502a67dd
  David Green authored Feb 05, 2021
  502a67dd
- [TargetLowering] Use Align in allowsMisalignedMemoryAccesses. · 11ef356d
  Craig Topper authored Feb 04, 2021
  11ef356d
- [WebAssembly] Support single-floating-point immediate value · 698c6b0a
  Dan Gohman authored Feb 04, 2021
  698c6b0a
Feb 04, 2021
- [AMDGPU] Add f16 to i1 CodeGen patterns. · 50578cf3
  Wen-Heng (Jack) Chung authored Feb 03, 2021
  50578cf3
- [AMDGPU][GlobalISel] Fix v2s16 right shifts · d84e5fda
  Jay Foad authored Feb 04, 2021
  d84e5fda
- [AMDGPU][GlobalISel] Use scalar min/max instructions · b3bb5c3e
  Jay Foad authored Feb 04, 2021
  b3bb5c3e
- AMDGPU: Add support for amdgpu-unsafe-fp-atomics attribute · 6054a456
  Konstantin Zhuravlyov authored Feb 04, 2021
  6054a456
- [AMDGPU] Save all lanes for reserved VGPRs · 6c59dc47
  Sebastian Neubauer authored Feb 04, 2021
  6c59dc47
Feb 03, 2021
- Revert "AMDGPU: Don't consider global pressure when bundling soft clauses" · 477e3fe4
  Matt Arsenault authored Feb 03, 2021
  477e3fe4
- [AMDGPU] Fix multiclass template parameter types. NFC. · 26ec7853
  Jay Foad authored Feb 03, 2021
  26ec7853
- AMDGPU: Move handling of allocation of fixed ABI inputs · 9719f170
  Matt Arsenault authored Jan 09, 2021
  9719f170
- Revert "[AMDGPU] Add a new Clamp Pattern to the GlobalISel Path." · d49efdc9
  Sebastian Neubauer authored Feb 03, 2021
  d49efdc9
- AMDGPU: Fix adding extra operands for i128 asm constraints · af2cbe8e
  Matt Arsenault authored Feb 02, 2021
  af2cbe8e
- AMDGPU: Don't consider global pressure when bundling soft clauses · 1e377a27
  Matt Arsenault authored Jan 30, 2021
  1e377a27
Feb 02, 2021
- [AMDGPU] Remove unused tmp register · 8b898b19
  Sebastian Neubauer authored Feb 02, 2021
  8b898b19
- [AMDGPU] Save fp/bp after csr saves · 6b6ae583
  Sebastian Neubauer authored Feb 01, 2021
  6b6ae583
- [AMDGPU][MC] Corrected parsing of optional modifiers · 586df384
  Dmitry Preobrazhensky authored Feb 02, 2021
  586df384
- Fold one-use variable into assert. NFCI. · 679ef22f
  Benjamin Kramer authored Feb 02, 2021
  679ef22f
- [AMDGPU] Mark epilog restores as frame-destroy · b91afa47
  Sebastian Neubauer authored Feb 01, 2021
  b91afa47
- Fixed includes. · faeed774
  Thomas Symalla authored Feb 01, 2021
  faeed774
- Fixed includes. · 6c85e98f
  Thomas Symalla authored Feb 01, 2021
  
  6c85e98f
- Reverted whitespace changes. · 09508d28
  Thomas Symalla authored Feb 01, 2021
  09508d28
- Added missing includes. · e630dd47
  Thomas Symalla authored Feb 01, 2021
  
  e630dd47
- Renamed med3 opcode, removed superfluous copy. · 602896b9
  Thomas Symalla authored Jan 26, 2021
  
  602896b9
- Removed the generic virtual register creations. Reworked the tests. · fa3e840d
  Thomas Symalla authored Jan 25, 2021
  
  fa3e840d
- Implemented a MED3_S32 GIR opcode. · c781c254
  Thomas Symalla authored Jan 18, 2021
  
  c781c254
- Added and used new target pseudo for v_cvt_pk_i16_i32, changes due to code review. · 6604d81e
  Thomas Symalla authored Jan 13, 2021
  
  6604d81e
- Formatting changes · 52bfb501
  Thomas Symalla authored Jan 12, 2021
  
  52bfb501
- Formatting changes. · 7d24026e
  Thomas Symalla authored Jan 12, 2021
  
  7d24026e
- Updating formatting changes. · bcd6c2d2
  Thomas Symalla authored Jan 12, 2021
  
  bcd6c2d2