Commits · eb3e09c9bf1d8808acf7d21f40ab0103121a0d60 · Roger Ferrer / llvm-epi · GitLab

Feb 25, 2022
- [SystemZ] [z/OS] Add support for generating huge (1 MiB) stack frames in XPLINK64 · eb3e09c9
  Neumann Hon authored Feb 25, 2022
  eb3e09c9
- [RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm · b20e80aa
  Chenbing Zheng authored Feb 25, 2022
  b20e80aa
- [RISCV] Update computeTargetABI from llc as well as clang · 4e115b7d
  Zakk Chen authored Feb 24, 2022
  4e115b7d
- [AggressiveInstCombine] Fix `TruncInstCombine` (fix f84d732f ) · 904a00d1
  Anton Afanasyev authored Feb 25, 2022
  904a00d1
- [AggressiveInstCombine] Add `phi` nodes support to `TruncInstCombine` · 0dd84013
  Anton Afanasyev authored Sep 15, 2021
  0dd84013
- [SLP] Fix for the min/max intrinsic cost. · 4bbc3290
  Vasileios Porpodas authored Feb 23, 2022
  4bbc3290
- [SLP][NFC] Test for a follow-up fix of the the vector min/max instrinsic cost calculation. · 6136f97c
  Vasileios Porpodas authored Feb 23, 2022
  6136f97c
- [RISCV] Add schedule class for Zbt extension · f37d21ed
  lian wang authored Feb 16, 2022
  f37d21ed
- [AMDGPU] Extend pre-emit peephole to redundantly masked VCC · 565af157
  Carl Ritson authored Feb 25, 2022
  565af157
- [ADT, CSSPGO] Specify set comparer · 79787b90
  Harald van Dijk authored Feb 25, 2022
  79787b90
- [OpaquePtr][AArch64] Use load/store value type instead of pointer type for ldnt1/stnt1 alignment · 6aa285eb
  Arthur Eubanks authored Feb 24, 2022
  
  6aa285eb
- [Debuginfod] Add BUILD_ID syntax to llvm-symbolizer. · 565add5a
  Daniel Thornburgh authored Feb 15, 2022
  565add5a
- [RISCV] Change rvv version to 1.0 and remove ratify notice · 0d058ed3
  Qihan Cai authored Feb 25, 2022
  0d058ed3
- [Symbolize] LRU cache binaries in llvm-symbolizer. · 02106ec1
  Daniel Thornburgh authored Feb 08, 2022
  02106ec1
- [Driver] Default CLANG_DEFAULT_PIE_ON_LINUX to ON · 3c4ed026
  Fangrui Song authored Feb 25, 2022
  3c4ed026
- [RISCV] Add 'i64' to some isel so tablegen will remove them for RV32. NFC · 506ac296
  Craig Topper authored Feb 24, 2022
  506ac296
Feb 24, 2022
- Revert "Encode address offsets of basic blocks relative to the end of the previous basic blocks." · aeec9671
  Rahman Lavaee authored Feb 24, 2022
  aeec9671
- [AArch64][x86] add tests for bitwise logic + shifts; NFC · ecf606cb
  Sanjay Patel authored Feb 24, 2022
  
  ecf606cb
- [RISCV] Add tests for (neg (abs X)) where the abs has an additional user. · 6159f059
  Craig Topper authored Feb 24, 2022
  
  6159f059
- [AMDGPU] Divergence-driven instruction selection for bitreverse · 05d79e35
  Jay Foad authored Feb 14, 2022
  05d79e35
- [CMake][WinMsvc] Replace MSVC_BASE/WINSDK_BASE with LLVM_WINSYSROOT · 140c13d3
  Yuanfang Chen authored Feb 24, 2022
  140c13d3
- [DAG] Attempt to fold bswap(shl(x,c)) -> zext(bswap(trunc(shl(x,c-bw/2)))) · 370ebc9d
  Simon Pilgrim authored Feb 24, 2022
  370ebc9d
- [AArch64] Regenerate dp1.ll test, NFC · b3e9fdd1
  David Green authored Feb 24, 2022
  b3e9fdd1
- [AMDGPU] Extend SILoadStoreOptimizer to handle global stores · 3279e440
  Stanislav Mekhanoshin authored Feb 22, 2022
  3279e440
- [AArch64] Async unwind - Always place the first LDP at the end when ReverseCSRRestoreSeq is true · 17e85cd4
  Momchil Velikov authored Feb 24, 2022
  17e85cd4
- [AMDGPU] Fix combined MMO in load-store merge · cefa1c5c
  Stanislav Mekhanoshin authored Feb 22, 2022
  cefa1c5c
- [X86] Introduce x86-cmov-converter-force-all · e38fc14c
  Amir Ayupov authored Feb 15, 2022
  e38fc14c
- [tblgen] Compress CompositeSequences to 1/8th of its size. NFCI. · dc7a624e
  Benjamin Kramer authored Feb 24, 2022
  
  dc7a624e
- [RISCV] Add Zbb RUN lines to neg-abs.ll. · 2aa1c6fc
  Craig Topper authored Feb 24, 2022
  
  2aa1c6fc
- [AArch64] Async unwind - helper functions to decide on CFI emission · 25e92920
  Momchil Velikov authored Feb 24, 2022
  25e92920
- [RISCV] Update some tests to use floating point ABI where it makes sense. · f69078b7
  Craig Topper authored Feb 24, 2022
  f69078b7
- [AArch64] Async unwind - do not schedule frame setup/destroy · fd7e59f0
  Momchil Velikov authored Feb 24, 2022
  fd7e59f0
- [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X). · a975ca97
  Craig Topper authored Feb 24, 2022
  a975ca97
- [SDAG] remove shift that is redundant with part of funnel shift · 4a3708cd
  Sanjay Patel authored Feb 24, 2022
  4a3708cd
- [OpenMP] Make section variable external to prevent collisions · 7aef8b37
  Joseph Huber authored Feb 24, 2022
  7aef8b37
- [InstCombine] try harder to preserve 'nsz' in fneg-of-select transform · 5379f76e
  Sanjay Patel authored Feb 24, 2022
  5379f76e
- [InstCombine] add test for fneg of select with FMF; NFC · 788b08a5
  Sanjay Patel authored Feb 24, 2022
  
  788b08a5
- [MIRParser] Diagnose too large align values in MachineMemOperands · 719bac55
  Jay Foad authored Feb 23, 2022
  719bac55
- [AArch64] Simplify and extend tests added in 0c5ea01b . · 59101501
  Florian Hahn authored Feb 24, 2022
  
  59101501
- [X86] LowerRotate - enable v8i16 ROTL/ROTR on all pre-SSE41 targets · a636801a
  Simon Pilgrim authored Feb 24, 2022
  a636801a