Commits · ed5a349b89e9ccc1c3dbe427de27d28e145f8203 · Roger Ferrer / llvm-epi · GitLab

Jun 16, 2022
- Make setSanitizerMetadata byval. · ed5a349b
  Mitch Phillips authored Jun 16, 2022
  ed5a349b
- [RISCV] Start merging demanded reasoning - starting with load/stores [nfc] · 2fa2cee6
  Philip Reames authored Jun 16, 2022
  2fa2cee6
- [RISCV] Add cost model for scalable scatter and gather · d764aa7f
  Philip Reames authored Jun 16, 2022
  d764aa7f
- Revert "[TableGen][DirectX] generate DXIL operation table with TableGen." · 911841f7
  Mitch Phillips authored Jun 16, 2022
  911841f7
- Move debug-only code inside LLVM_DEUG to prevent unused variable warnings. · df6087ee
  Sterling Augustine authored Jun 16, 2022
  
  df6087ee
- [TableGen][DirectX] generate DXIL operation table with TableGen. · 46fcdf23
  Xiang Li authored Jun 16, 2022
  46fcdf23
- [MergeFunctions] Preserve symbols used llvm.used/llvm.compiler.used · caa2a829
  Amanieu d'Antras authored Jun 16, 2022
  caa2a829
- [gn build] Port 6ff49af3 · decb600b
  LLVM GN Syncbot authored Jun 16, 2022
  
  decb600b
- [Delinearization] Refactoring of fixed-size array delinearization · 4c77d027
  Congzhe Cao authored Jun 16, 2022
  4c77d027
- [TargetTransformInfo] Added an opt/llc option for cache line size · a9dccb00
  Congzhe Cao authored Jun 16, 2022
  a9dccb00
- Reland "[PS4/PS5][profiling] Go back to the old way of doing a runtime hook" · 3f603025
  Paul Robinson authored Jun 16, 2022
  3f603025
- [AMDGPU] gfx11 new dot instruction codegen support · 2d43de13
  Joe Nash authored Jun 15, 2022
  2d43de13
- [AMDGPU] Add GFX11 codegen for llvm.amdgcn.mov.dpp8 · 7e681ef3
  Jay Foad authored Jun 16, 2022
  7e681ef3
- Revert "[PS4/PS5][profiling] Go back to the old way of doing a runtime hook" · d0e60b6d
  Paul Robinson authored Jun 16, 2022
  d0e60b6d
- Reland "[NFC] Precommited tests from D73000" · cb111ef0
  Dávid Bolvanský authored Jun 16, 2022
  
  cb111ef0
- Revert "[NFC] Precommited tests from D73000" · ed72f40d
  Dávid Bolvanský authored Jun 16, 2022
  ed72f40d
- [PS4/PS5][profiling] Go back to the old way of doing a runtime hook · 39fb8434
  Paul Robinson authored Jun 10, 2022
  39fb8434
- [PS5] Set address sanitizer shadow offset · 593fa3ab
  Paul Robinson authored Jun 16, 2022
  
  593fa3ab
- [PS5] Emit ud2 for ubsan trap · ff0122dc
  Paul Robinson authored Jun 16, 2022
  
  ff0122dc
- [NFC] Precommited tests from D73000 · 814c9f4e
  Dávid Bolvanský authored Jun 16, 2022
  
  814c9f4e
- [RISCV] Avoid reducing etype just to initialize lane 0 of an undef vector · 89a11ebd
  Philip Reames authored Jun 16, 2022
  89a11ebd
- [PS5] Use same debug trap instruction as PS4 · 77b00098
  Paul Robinson authored Jun 16, 2022
  
  77b00098
- Fix a bug introduced by the move of AddressRanges.h into ADT. · 838a57e1
  Greg Clayton authored Jun 14, 2022
  838a57e1
- [SLP]Use original vector if need to shuffle truncated root. · 76782a65
  Alexey Bataev authored Jun 16, 2022
  76782a65
- [RISCV] Fix a typo in an intrinsic name · b91a9f48
  Philip Reames authored Jun 16, 2022
  b91a9f48
- [AMDGPU] Add GFX11 llvm.amdgcn.ds.add.gs.reg.rtn / llvm.amdgcn.ds.sub.gs.reg.rtn intrinsics · 36ec1fca
  Jay Foad authored Jun 16, 2022
  36ec1fca
- [AMDGPU] GFX11 CodeGen support for MIMG instructions · c155a944
  Jay Foad authored Jun 14, 2022
  c155a944
- [AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row · 445a483b
  Jay Foad authored Jun 13, 2022
  445a483b
- [AArch64] Regenerate 3 codegen test files. NFC · 527b8ccd
  David Green authored Jun 16, 2022
  
  527b8ccd
- [docs][OpaquePtr] Add detail to motivations behind opaque pointers · 47bfc365
  Arthur Eubanks authored May 24, 2022
  47bfc365
- [RISCV] Merge TIED_TU and TIED instructions for VWADD_W/VWSUB_W by using policy operand. · 6716195c
  Craig Topper authored Jun 16, 2022
  6716195c
- [RISCV] Reorder function definitions to reduce upcoming diff [nfc] · 6ed81ec1
  Philip Reames authored Jun 16, 2022
  
  6ed81ec1
- [MLInliner] Don't inline call sites in unreachable basic blocks · 7f24e574
  Mircea Trofin authored Jun 15, 2022
  7f24e574
- [RISCV] Use TAIL_AGNOSTIC in riscv_fma_vl patterns. · 912a5172
  Craig Topper authored Jun 16, 2022
  912a5172
- Allow bitwidth difference when checking for isOneOrOneSplat. · 55311801
  Adrian Tong authored Jun 08, 2022
  55311801
- [RISCV] Split DemandedField logic in advance of reuse in dataflow [nfc] · 27c61d03
  Philip Reames authored Jun 16, 2022
  27c61d03
- [PowerPC] Fix LQ-STQ instructions to use correct offset and base · 3d259a82
  Ahsan Saghir authored Jun 01, 2022
  3d259a82
- [RISCV] Move getSEWLMULRatio out of VSETVLIInfo [nfc] · 37fa5850
  Philip Reames authored Jun 16, 2022
  
  37fa5850
- [RISCV] Use TAIL_UNDISTURBED_MASK_UNDISTURBED for riscv_slidedown_vl unless the merge op is undef. · b34e3f40
  Craig Topper authored Jun 15, 2022
  b34e3f40
- Replace to_hexString by touhexstr [NFC] · b62e3a73
  Corentin Jabot authored Jun 16, 2022
  b62e3a73