Commits · ed721e32cdc877a0f37c5cb48c735e9890e68331 · Roger Ferrer / llvm-epi · GitLab

Nov 22, 2017
- [AArch64] Adjust the cost model for Exynos M1 and M2 · ed721e32
  Evandro Menezes authored Nov 22, 2017
  ed721e32
- [Hexagon] Implement buildVector32 and buildVector64 as utility functions · 942fa163
  Krzysztof Parzyszek authored Nov 22, 2017
  942fa163
- [Hexagon] Add patterns to select A2_combine_ll and its variants · b9f33b32
  Krzysztof Parzyszek authored Nov 22, 2017
  b9f33b32
- [Hexagon] Remove trailing spaces, NFC · 6acecc96
  Krzysztof Parzyszek authored Nov 22, 2017
  6acecc96
- [X86] Support v32i16/v64i8 CTLZ using lookup table. · 726968d6
  Craig Topper authored Nov 22, 2017
  726968d6
- [X86] Move the BITALG setOperationAction code into the hasBWI section to match... · 8ad81865
  Craig Topper authored Nov 22, 2017
  8ad81865
- [X86] Sink the MGATHER setOperationActions for AVX2 into the AVX block where... · e15cc168
  Craig Topper authored Nov 22, 2017
  e15cc168
- [X86] Spell penryn correctly in some comments. NFC · d5b5bbe2
  Craig Topper authored Nov 22, 2017
  d5b5bbe2
- [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument · c5962266
  Yaxun Liu authored Nov 22, 2017
  c5962266
- AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOptimizer · dd059c16
  Nicolai Haehnle authored Nov 22, 2017
  dd059c16
- [X86] Add an X86ISD::MSCATTER node for consistency with the X86ISD::MGATHER. · ee74044f
  Craig Topper authored Nov 22, 2017
  ee74044f
- [X86] Lower all ISD::MGATHER nodes to X86ISD:MGATHER. · c1e7b3f6
  Craig Topper authored Nov 22, 2017
  c1e7b3f6
Nov 21, 2017
- [Hexagon] Add HexagonSubtarget::getVectorLength() · 705795b8
  Krzysztof Parzyszek authored Nov 21, 2017
  705795b8
- [Hexagon] Make sure that RDF does not remove EH_LABELs · fc0a1812
  Krzysztof Parzyszek authored Nov 21, 2017
  fc0a1812
- [X86] Allow vpclmulqdq instructions to be commuted during isel to allow load folding. · ba150ef6
  Craig Topper authored Nov 21, 2017
  ba150ef6
- [X86] Add BITALG, VAES, VBMI2, VNNI, VPCLMULQDQ, and VPOPCNTDQ instructions to icelake CPU. · a890570b
  Craig Topper authored Nov 21, 2017
  a890570b
- Avoid unecessary opsize byte in segment move to memory · 61ffc9c0
  Nirav Dave authored Nov 21, 2017
  61ffc9c0
- [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects. · fe97d736
  Chad Rosier authored Nov 21, 2017
  fe97d736
- [ARM] Remove pre-UAL FLDM/FSTM aliases · 9cb89f66
  Oliver Stannard authored Nov 21, 2017
  9cb89f66
- [ARM] Don't omit non-default predication code · 1e6d4b9e
  Oliver Stannard authored Nov 21, 2017
  1e6d4b9e
- [Asm] Improve "too few operands" errors · 1e73e95f
  Oliver Stannard authored Nov 21, 2017
  1e73e95f
- [ARM] Add diagnostics for SPR/DPR lists · d6ca9879
  Oliver Stannard authored Nov 21, 2017
  d6ca9879
- [RISCV][NFC] Remove unnecessary {} around single statement if block · e2f664e1
  Alex Bradbury authored Nov 21, 2017
  e2f664e1
- [X86][XOP] Add missing scheduler classes to XOP instructions · e1490afa
  Simon Pilgrim authored Nov 21, 2017
  e1490afa
- [RISCV][NFC] Clean up RISCVDAGToDAGISel::Select · 9caefe36
  Alex Bradbury authored Nov 21, 2017
  9caefe36
- [ARM] Use SEH exceptions on thumbv7-windows · 51d82696
  Martell Malone authored Nov 21, 2017
  51d82696
- [X86][LWP] Add missing LWP itinerary class to lwpins instructions · a93dea53
  Simon Pilgrim authored Nov 21, 2017
  a93dea53
- [MI scheduler] Fix VADD and VSUB in cortex-a57 model · 6bc35a93
  Eugene Leviant authored Nov 21, 2017
  6bc35a93
- [x86][icelake]BITALG · 5c7fe5df
  Coby Tayree authored Nov 21, 2017
  5c7fe5df
- [x86][icelake]VNNI · 3880f2a3
  Coby Tayree authored Nov 21, 2017
  3880f2a3
- [x86][icelake]vbmi2 · 71e37cc9
  Coby Tayree authored Nov 21, 2017
  71e37cc9
- [x86][icelake]vpclmulqdq introduction · 7ca5e587
  Coby Tayree authored Nov 21, 2017
  7ca5e587
- [x86][icelake]VAES introduction · 2a1c02fc
  Coby Tayree authored Nov 21, 2017
  2a1c02fc
- [RISCV] Use register X0 (ZERO) for constant 0 · 0c7b3643
  Alex Bradbury authored Nov 21, 2017
  0c7b3643
- [RISCV] Support and tests for a variety of additional LLVM IR constructs · ffc435e9
  Alex Bradbury authored Nov 21, 2017
  ffc435e9
- [RISCV] Implement lowering of ISD::SELECT · 65385167
  Alex Bradbury authored Nov 21, 2017
  65385167
- [X86] Simplify type constraints for AVX2 masked gather. · f26fc823
  Craig Topper authored Nov 21, 2017
  f26fc823
- [X86] Simplify the predicates for avx2 masked gather patterns. · d219220b
  Craig Topper authored Nov 21, 2017
  d219220b
- [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type · 3cea36f0
  Yaxun Liu authored Nov 21, 2017
  3cea36f0
- Add default values for member functions. · 9596bdb8
  Richard Trieu authored Nov 21, 2017
  9596bdb8