Commits · ee1e71e576384d0481ba05e90453ba8209bdd6f5 · Roger Ferrer / llvm-epi · GitLab

Dec 17, 2017
- [X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 extractions. · ee1e71e5
  Craig Topper authored Dec 17, 2017
  ee1e71e5
- [X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32. · c0c2d19e
  Craig Topper authored Dec 17, 2017
  c0c2d19e
- [X86][AVX] lowerVectorShuffleAsBroadcast - aggressively peek through BITCASTs · 4c9e8215
  Simon Pilgrim authored Dec 16, 2017
  4c9e8215
Dec 16, 2017
- [X86][AVX] Fix failed broadcast fold · f3b6da00
  Simon Pilgrim authored Dec 16, 2017
  f3b6da00
- [X86] When using vpopcntdq for ctpop of v8i16 vectors, only promote to v8i32. · 1260a4e8
  Craig Topper authored Dec 16, 2017
  1260a4e8
- [X86] Add 128 and 256-bit VPOPCNTDQ instructions. Adjust some tablegen classes LZCNT/POPCNT. · c0896059
  Craig Topper authored Dec 16, 2017
  c0896059
Dec 15, 2017
- [SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-constant index · 3fb83866
  Craig Topper authored Dec 15, 2017
  3fb83866
- Fix for bug PR35549 - Repeated schedule comments. · 22f0742d
  Andrew V. Tischenko authored Dec 15, 2017
  22f0742d
- [CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output · 0b5bdcea
  Francis Visoiu Mistrih authored Dec 15, 2017
  0b5bdcea
- [X86] Add RTM schedule tests · 5009a1c7
  Simon Pilgrim authored Dec 15, 2017
  5009a1c7
- [X86] Add MWAITX/MONITORX schedule tests · 78643123
  Simon Pilgrim authored Dec 15, 2017
  78643123
- [X86] Add XOP schedule tests · e662fa37
  Simon Pilgrim authored Dec 15, 2017
  e662fa37
- [X86] Add AVX512 VPOPCNTDQ schedule tests · 0c1e0dbb
  Simon Pilgrim authored Dec 15, 2017
  0c1e0dbb
- [X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering. · 7cfacbf6
  Craig Topper authored Dec 15, 2017
  7cfacbf6
- FastISel: support no-PLT PIC calls on ELF x86_64 · 05e285bc
  Saleem Abdulrasool authored Dec 15, 2017
  05e285bc
Dec 14, 2017
- [X86] Don't zero the upper bits of the k-register before extracting a single bit from a vXi1. · 600f1ba3
  Craig Topper authored Dec 14, 2017
  600f1ba3
- [AVX512] Adding support for load truncate store of I1 · 19fd217e
  Michael Zuckerman authored Dec 14, 2017
  19fd217e
- [X86] Add FMA4 schedule tests · 9f19fe51
  Simon Pilgrim authored Dec 14, 2017
  9f19fe51
- [X86] Add FMA3 schedule tests · 7424de20
  Simon Pilgrim authored Dec 14, 2017
  7424de20
- [CodeGen] Print global addresses as @foo in both MIR and debug output · 5df3bbf3
  Francis Visoiu Mistrih authored Dec 14, 2017
  5df3bbf3
- [CodeGen] Print external symbols as $symbol in both MIR and debug output · e76c5fcd
  Francis Visoiu Mistrih authored Dec 14, 2017
  e76c5fcd
- [X86] Make ANY_EXTEND from vXi1 Custom for more types. · 8cdf7c0e
  Craig Topper authored Dec 14, 2017
  8cdf7c0e
- [SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 for AVX512F. · eab2d466
  Craig Topper authored Dec 14, 2017
  eab2d466
- [SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into... · cf77203f
  Craig Topper authored Dec 14, 2017
  cf77203f
Dec 13, 2017
- [X86] Add missing MULX32 schedule test · 5af7a6dd
  Simon Pilgrim authored Dec 13, 2017
  5af7a6dd
- [X86] Add CLWB schedule test · 49dbfe7d
  Simon Pilgrim authored Dec 13, 2017
  49dbfe7d
- [X86] Move ADX schedule tests out of schedule-x86_64.ll · 14318c5b
  Simon Pilgrim authored Dec 13, 2017
  14318c5b
- [X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests · f02a39c3
  Simon Pilgrim authored Dec 13, 2017
  f02a39c3
- Regenerate test-shrink.ll test results. NFC · a402e514
  Amaury Sechet authored Dec 13, 2017
  a402e514
- [X86] Add RET/RETF schedule tests · 542a7118
  Simon Pilgrim authored Dec 13, 2017
  542a7118
- [X86] Add POP/PUSH schedule tests · c1bd968c
  Simon Pilgrim authored Dec 13, 2017
  c1bd968c
- [X86] Add PREFETCH schedule tests · 0bd31a83
  Simon Pilgrim authored Dec 13, 2017
  0bd31a83
- [X86] Add XCHG schedule tests · 1df18ee3
  Simon Pilgrim authored Dec 13, 2017
  1df18ee3
- [X86] Add MOVNTI schedule tests · 9d9f1701
  Simon Pilgrim authored Dec 13, 2017
  9d9f1701
- [X86] Add ENTER/LEAVE schedule tests · 88e6f83f
  Simon Pilgrim authored Dec 13, 2017
  88e6f83f
- [X86] Add IMUL schedule tests · cef5b64f
  Simon Pilgrim authored Dec 13, 2017
  cef5b64f
- [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests · f00ea1b4
  Simon Pilgrim authored Dec 13, 2017
  f00ea1b4
- [X86] Add ARPL/BOUND schedule tests · 46ec195d
  Simon Pilgrim authored Dec 13, 2017
  46ec195d
- [X86][SSE] MOVMSK only uses the sign bit from each vector element · f51f4d36
  Simon Pilgrim authored Dec 13, 2017
  f51f4d36
- [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output · 26ae8a65
  Francis Visoiu Mistrih authored Dec 13, 2017
  26ae8a65