Commits · ee34d9b210cb5a6d14fe069e2e2ae75b0548dba9 · Roger Ferrer / llvm-epi · GitLab

Sep 29, 2020
- [InstCombine] use redirect of input file in regression tests; NFC · ee34d9b2
  Sanjay Patel authored Sep 29, 2020
  ee34d9b2
- [InstCombine] Add some basic trunc(lshr(zext(x),c)) tests · 7a55989d
  Simon Pilgrim authored Sep 29, 2020
  7a55989d
- [InstCombine] Inherit exact flags on extended shifts in trunc (lshr (sext A), C) --> (ashr A, C) · 89a8a0c9
  Simon Pilgrim authored Sep 29, 2020
  89a8a0c9
- [InstCombine] Add exact shift tests missed in D88475 · 042f22bd
  Simon Pilgrim authored Sep 29, 2020
  042f22bd
- [SDAG] Do not convert undef to 0 when folding CONCAT/BUILD_VECTOR · db04bec5
  Krzysztof Parzyszek authored Sep 24, 2020
  db04bec5
- [InstCombine] visitTrunc - trunc (lshr (sext A), C) --> (ashr A, C) non-uniform support · 14ff38e2
  Simon Pilgrim authored Sep 29, 2020
  14ff38e2
- Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access" · 8b08fa01
  Mirko Brkusanin authored Sep 29, 2020
  8b08fa01
- [SystemZ] Don't emit PC-relative memory accesses to unaligned symbols. · 75a5febe
  Jonas Paulsson authored Sep 10, 2020
  75a5febe
- [AArch64] Add BTI to CFI jumptables. · c5a4900e
  Daniel Kiss authored Sep 29, 2020
  c5a4900e
- [IndVarSimplify] Fix Modified status for removal of overflow intrinsics · e6f332ef
  David Stenberg authored Sep 29, 2020
  e6f332ef
- [msan] Fix llvm.abs.v intrinsic · 4aa6abe4
  Vitaly Buka authored Sep 29, 2020
  4aa6abe4
- [msan] Add test for vector abs intrinsic · 1fd9a146
  Vitaly Buka authored Sep 29, 2020
  
  1fd9a146
- [InstCombine] Add trunc(lshr(sext(x),c)) non-uniform vector tests · 324df266
  Simon Pilgrim authored Sep 29, 2020
  
  324df266
- [LoopDeletion] Forget loop before setting values to undef · 60b85209
  Florian Hahn authored Sep 29, 2020
  60b85209
- Revert "OpaquePtr: Add type to sret attribute" · eb9f7c28
  Tres Popp authored Sep 29, 2020
  eb9f7c28
- [IsKnownNonZero] Handle the case with non-constant phi nodes · 297ec611
  Serguei Katkov authored Sep 25, 2020
  297ec611
- Revert "Recommit "[SCCP] Do not replace deref'able ptr with un-deref'able one."" · b76df593
  Florian Hahn authored Sep 29, 2020
  b76df593
- Recommit "[SCCP] Do not replace deref'able ptr with un-deref'able one." · 86a20d9e
  Florian Hahn authored Sep 28, 2020
  86a20d9e
- [X86] Add computeKnownBits support for PEXT. · 82da0cab
  Craig Topper authored Sep 28, 2020
  82da0cab
- [X86] Add known bits test for PEXT. NFC · a4b1fdec
  Craig Topper authored Sep 28, 2020
  
  a4b1fdec
- [IndVars] Remove exiting conditions that are trivially true/false · d266fd96
  Max Kazantsev authored Sep 29, 2020
  d266fd96
- BPF: explicitly specify bpfel triple for certain tests · ca1ce397
  Yonghong Song authored Sep 28, 2020
  ca1ce397
- [AArch64][GlobalISel] Scalarize <2 x s64> G_MUL since we don't have native support for it. · b9f2b3bc
  Amara Emerson authored Sep 28, 2020
  b9f2b3bc
- [RegisterCoalescer] Pass Undefs to extendToIndices() · 73805329
  Ruiling Song authored Sep 15, 2020
  73805329
- BPF: move AbstractMemberAccess and PreserveDIType passes to EP_EarlyAsPossible · 54d9f743
  Yonghong Song authored Sep 02, 2020
  54d9f743
- [CVP] Allow two transforms in one invocation · e46d74b5
  Philip Reames authored Sep 28, 2020
  e46d74b5
Sep 28, 2020
- [X86] Add support for calling SimplifyDemandedBits on the input of PDEP with a constant mask. · e53196b1
  Craig Topper authored Sep 28, 2020
  e53196b1
- [X86] Add tests for D87883. NFC · e5ef523e
  Craig Topper authored Sep 28, 2020
  
  e5ef523e
- [GlobalISel] Add support for lowering of vector G_SELECT and use for AArch64. · 08232190
  Amara Emerson authored Sep 26, 2020
  08232190
- Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> ... · 5aa56b24
  Amara Emerson authored Sep 28, 2020
  5aa56b24
- [X86] Use inlineasm flag output for the _bittest* intrinsics. · 288c5776
  Craig Topper authored Sep 28, 2020
  288c5776
- [InstCombine] Regenerate cast tests. NFC. · 2f768a68
  Simon Pilgrim authored Sep 28, 2020
  
  2f768a68
- [COFF] Aliases resolve directly to defined external targets · bd19876d
  Eric Astor authored Sep 28, 2020
  bd19876d
- [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types · 01569142
  Baptiste Saleil authored Sep 28, 2020
  01569142
- Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> ... · 6c816832
  Amara Emerson authored Sep 28, 2020
  6c816832
- [AddressSanitizer] Copy type metadata to prevent miscompilation · 06e68f05
  Dominic Chen authored Sep 26, 2020
  06e68f05
- [InstCombine] Add trunc(shr(trunc(x),c)) non-uniform vector tests · d047bb1c
  Simon Pilgrim authored Sep 28, 2020
  
  d047bb1c
- [AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect · 9d7ec46f
  Jessica Paquette authored Sep 23, 2020
  9d7ec46f
- [AArch64][GlobalISel] Support shifted register form in emitTST · f55a5186
  Jessica Paquette authored Sep 10, 2020
  f55a5186
- [GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y) · a52e7801
  Jessica Paquette authored Sep 18, 2020
  a52e7801