Commits · eeb63944e4a4000f8c7f0860666c6862f53eff18 · Roger Ferrer / llvm-epi · GitLab

Feb 08, 2020
- [LegalizeTypes][ARM][AArch64][PowerPC][RISCV][X86] Use BUILD_PAIR to return... · eeb63944
  Craig Topper authored Feb 07, 2020
  eeb63944
- [X86] X86InstComments - add FMA4 comments · 4aa7b9cc
  Simon Pilgrim authored Feb 08, 2020
  4aa7b9cc
- [X86] Standardize BROADCAST enum names (PR31079) · 10417ad2
  Simon Pilgrim authored Feb 08, 2020
  10417ad2
- [X86] Standardize VPSLLDQ/VPSRLDQ enum names (PR31079) · 0ed79e9b
  Simon Pilgrim authored Feb 08, 2020
  0ed79e9b
- Revert "Support -fstack-clash-protection for x86" · 658495e6
  serge-sans-paille authored Feb 08, 2020
  658495e6
- Revert "[ARM] Improve codegen of volatile load/store of i64" · af2a3845
  Victor Campos authored Feb 08, 2020
  af2a3845
- Support -fstack-clash-protection for x86 · e2290177
  serge_sans_paille authored Sep 09, 2019
  e2290177
- ArrayRef'ize spillCalleeSavedRegisters. NFCI. · e4230a9f
  Benjamin Kramer authored Feb 08, 2020
  
  e4230a9f
- [X86][SSE] Add X86ISD::FRCP handling to isNegatibleForFree · 7f5b3fa7
  Simon Pilgrim authored Feb 08, 2020
  7f5b3fa7
- [TargetLowering] Remove isDesirableToCombineBuildVectorToShuffleTruncate target hook. NFC. · 4229f12a
  Simon Pilgrim authored Feb 08, 2020
  4229f12a
- [WebAssembly] Fix signature of __powitf2 libcall · caeb6cfb
  Sam Clegg authored Feb 07, 2020
  caeb6cfb
- [WebAssembly] Add debug info to insts in Emscripten SjLj · 5b5cbfe1
  Heejin Ahn authored Feb 06, 2020
  5b5cbfe1
Feb 07, 2020
- Reland "[AMDGPU] Fix data race on RegisterBank initialization." · 6556c615
  Huihui Zhang authored Feb 07, 2020
  
  6556c615
- Reland "[ARM] Fix data race on RegisterBank initialization." · ae391054
  Huihui Zhang authored Feb 07, 2020
  ae391054
- Reland "[AArch64] Fix data race on RegisterBank initialization." · 2491fd0e
  Huihui Zhang authored Feb 07, 2020
  2491fd0e
- [PowerPC] Fix spilling of vector registers in PEI of EH aware functions · 26bf877e
  Nemanja Ivanovic authored Feb 07, 2020
  26bf877e
- Revert "Support -fstack-clash-protection for x86" · b03c3d8c
  Nico Weber authored Feb 07, 2020
  b03c3d8c
- AMDGPU: Enhancement on FDIV lowering in AMDGPUCodeGenPrepare · 884acbb9
  Changpeng Fang authored Feb 07, 2020
  884acbb9
- [AArch64][GlobalISel] Reland SLT/SGT TBNZ optimization · 609a489e
  Jessica Paquette authored Feb 07, 2020
  609a489e
- AMDGPU: Limit the search in finding the instruction pattern for v_swap generation. · 6370c7c1
  Changpeng Fang authored Feb 07, 2020
  6370c7c1
- Support -fstack-clash-protection for x86 · 4a1a0690
  serge_sans_paille authored Sep 09, 2019
  4a1a0690
- [PowerPC] Create a FixedStack object for CR save in linkage area. · 88073d40
  Sean Fertile authored Jan 27, 2020
  88073d40
- [X86] Handle SETB_C32r/SETB_C64r in flag copy lowering the same way we handle SBB · 27857874
  Craig Topper authored Feb 07, 2020
  27857874
- [GlobalISel] Add buildMerge with SrcOp initializer list · 7df5fc9e
  Petar Avramovic authored Feb 07, 2020
  7df5fc9e
- [x86] don't create an unused constant vector · de6f7eb4
  Sanjay Patel authored Feb 07, 2020
  de6f7eb4
- [X86] isNegatibleForFree - allow pre-legalized FMA negation · c9600103
  Simon Pilgrim authored Feb 07, 2020
  c9600103
- AMDGPU/GlobalISel: Fix move s.buffer.load to VALU · 2f885cbe
  Matt Arsenault authored Jan 31, 2020
  2f885cbe
- GlobalISel: Fix narrowing of G_CTPOP · 3b198518
  Matt Arsenault authored Feb 06, 2020
  3b198518
- GlobalISel: Fix lowering of G_CTLZ/G_CTTZ · 8de2dad9
  Matt Arsenault authored Feb 06, 2020
  8de2dad9
- [AArch64] Predictably disassemble system registers with the same encoding · a2531081
  Momchil Velikov authored Feb 07, 2020
  a2531081
- Revert "Support -fstack-clash-protection for x86" · f6d98429
  serge-sans-paille authored Feb 07, 2020
  f6d98429
- [NFC] Introduce an API for MemOp · f85d3408
  Guillaume Chatelet authored Feb 04, 2020
  f85d3408
- [ARM][ASMParser] Refuse equal RdHi/RdLo for s/umlal, smlsl, s/umull, umaal · e8c3a6c2
  Pierre van Houtryve authored Feb 05, 2020
  e8c3a6c2
- Support -fstack-clash-protection for x86 · 39f50da2
  serge_sans_paille authored Sep 09, 2019
  39f50da2
- [Target][AArch64] Remove non-existing system registers ICH_VSEIR_EL2 &... · 56d81d45
  Pierre van Houtryve authored Feb 05, 2020
  56d81d45
- [X86] Turn vXi1 any_extends into sign_extends in PreprocessISelDAG and remove some isel patterns. · ae4e4986
  Craig Topper authored Feb 06, 2020
  ae4e4986
- [X86] Use SelectionDAG::getAllOnesConstant to simplify some code. NFC · 3f62028f
  Craig Topper authored Feb 06, 2020
  
  3f62028f
- AMDGPU/GlobalISel: Fix non-pow-2 add/sub/mul for 16-bit insts · 6a570dc5
  Matt Arsenault authored Feb 06, 2020
  6a570dc5
- [AMDGPU] Cleanup assumptions about generated subregs · cacc3b7a
  Stanislav Mekhanoshin authored Feb 06, 2020
  cacc3b7a
- Revert "AMDGPU: Limit the search in finding the instruction pattern for v_swap generation." · 2863c269
  Stanislav Mekhanoshin authored Feb 06, 2020
  2863c269