Commits · ef8f3b5a78e9653917a5394a978cbc5ce7284a38 · Roger Ferrer / llvm-epi · GitLab

Aug 25, 2020
- AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors · ef8f3b5a
  Matt Arsenault authored Aug 16, 2020
  ef8f3b5a
- [ARM][CGP] Fix scalar condition selects for MVE · 5b7e27a4
  David Green authored Aug 25, 2020
  5b7e27a4
- [SVE] Lower scalable vector ISD::FNEG operations. · 73ac3c0e
  Paul Walker authored Aug 21, 2020
  73ac3c0e
- [X86] Support -march=sapphirerapids · e02d081f
  Freddy Ye authored Aug 25, 2020
  e02d081f
- [DAGCombine]: Fold X/Sqrt(X) to Sqrt(X) · 62e91bf5
  Venkataramanan Kumar authored Aug 24, 2020
  62e91bf5
- [x86][AArch64] adjust fast-math-flags in tests; NFC · a74dc598
  Sanjay Patel authored Aug 24, 2020
  a74dc598
Aug 24, 2020
- AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands. · 77e5a195
  Matt Arsenault authored Aug 12, 2020
  77e5a195
- [PowerPC] Do not use FISel for calls and TOC-based accesses with PC-Rel · 075a92de
  Nemanja Ivanovic authored Aug 24, 2020
  075a92de
- [X86] Copy the tuning features and scheduler model from pentium4/x86-64 to generic · f7c87b7e
  Craig Topper authored Aug 24, 2020
  f7c87b7e
- AMDGPU: Have a few selection failure tests check both paths · 05a3c884
  Matt Arsenault authored Jul 29, 2020
  05a3c884
- [PowerPC] Handle SUBFIC in reg+reg -> reg+imm transformation · c485343c
  Nemanja Ivanovic authored Aug 24, 2020
  c485343c
- [PowerPC] Extend custom lower of vector truncate to handle wider input · b6d7ed46
  Roland Froese authored Aug 24, 2020
  b6d7ed46
- AMDGPU: Add flag to disable promotion of uniform i16 ops · 75e6f0b3
  Matt Arsenault authored Jul 31, 2020
  75e6f0b3
- TableGen/GlobalISel: Allow inst matcher to check multiple opcodes · 116affb1
  Matt Arsenault authored Aug 02, 2020
  116affb1
- [LegalizeTypes][X86] Add ROTL/ROTR to WidenVectorResult. · 43465a43
  Craig Topper authored Aug 24, 2020
  43465a43
- [SDAG] Convert FSHL <--> FSHR if the target only supports one of them · a5220676
  Jay Foad authored Aug 24, 2020
  a5220676
- [PowerPC] Add clang options to control MMA support · 512e256c
  Baptiste Saleil authored Aug 24, 2020
  512e256c
- AMDGPU/GlobalISel: Use different technique for sample v3s16 values · bdb25b3c
  Matt Arsenault authored Jul 16, 2020
  bdb25b3c
- AMDGPU/GlobalISel: Add baseline, failing unmerge tests · 9b3222d5
  Matt Arsenault authored Aug 19, 2020
  
  9b3222d5
- AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr · 70cd9f5b
  Matt Arsenault authored Aug 16, 2020
  70cd9f5b
- GlobalISel: Reduce G_SHL width if source is extension · e1644a37
  Matt Arsenault authored Aug 15, 2020
  e1644a37
- [SelectionDAG] Fix miscompile bug in expandFunnelShift · 7a4e26ad
  Bjorn Pettersson authored Aug 22, 2020
  7a4e26ad
- [PowerPC] Support lowering int-to-fp on ppc_fp128 · 1bc45b2f
  Qiu Chaofan authored Aug 24, 2020
  1bc45b2f
- [PowerPC] Allow constrained FP intrinsics in mightUseCTR · fed6107d
  Qiu Chaofan authored Aug 24, 2020
  fed6107d
- [DAGCombine] Remove dead node when it is created by getNegatedExpression · 960cbc53
  QingShan Zhang authored Aug 24, 2020
  960cbc53
- [PowerPC] Support constrained vector fp/int conversion · 41ba9d77
  Qiu Chaofan authored Aug 24, 2020
  41ba9d77
Aug 23, 2020
- [X86][FastISel] Support materializing floating-point constants for large code model & PIC · bef68415
  Fangrui Song authored Aug 23, 2020
  bef68415
Aug 22, 2020
- [AArch64] add tests for store merge of truncs; NFC · c1dc44f9
  Sanjay Patel authored Aug 22, 2020
  
  c1dc44f9
- GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS · 901e3317
  Matt Arsenault authored Aug 03, 2020
  901e3317
Aug 21, 2020
- [AMDGPU] Avoid sorting stalls in regbank-reassign · 9a9a092e
  Stanislav Mekhanoshin authored Aug 20, 2020
  9a9a092e
- [PowerPC] Support constrained scalar sitofp/uitofp · a5b7b8cc
  Qiu Chaofan authored Aug 22, 2020
  a5b7b8cc
- [PowerPC][PCRelative] Thread Local Storage Support for Initial Exec · 365f861c
  Kamau Bridgeman authored Jun 16, 2020
  365f861c
- [AIX][XCOFF] emit symbol visibility for xcoff object file. · a0818689
  diggerlin authored Aug 21, 2020
  a0818689
- [SVE] Lower fixed length UDIV to scalable · 36dbb8fc
  Cameron McInally authored Aug 21, 2020
  36dbb8fc
- [PowerPC] Pre-commit FISel with PC-Rel test · 519b0e3e
  Nemanja Ivanovic authored Aug 21, 2020
  519b0e3e
- [RISCV] Fix inaccurate annotations on PseudoBRIND · 9e6c09c0
  lewis-revill authored Aug 21, 2020
  9e6c09c0
- [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag · 0654ff70
  Mirko Brkusanin authored Aug 21, 2020
  0654ff70
- [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores · d17ea67b
  Mirko Brkusanin authored Aug 21, 2020
  d17ea67b
- [AMDGPU] Reorganize GCN subtarget features for unaligned access · f5cd7ec9
  Mirko Brkusanin authored Aug 21, 2020
  f5cd7ec9
- [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores · 5bd1febe
  Mirko Brkusanin authored Aug 21, 2020
  5bd1febe