Commits · f192594956281744f67c4535bf2cce922f155aff · Roger Ferrer / llvm-epi · GitLab

Oct 02, 2020
- [AArch64] Generate dot for v16i8 sum reduction to i32 · f1925949
  Vinay Madhusudan authored Oct 02, 2020
  f1925949
- Fix interaction between stack alignment and inline-asm stack clash protection · f2c6bfa3
  serge-sans-paille authored Jul 23, 2020
  f2c6bfa3
- [AArch64] Add CPU Cortex-R82 · 8825fec3
  Sjoerd Meijer authored Oct 01, 2020
  8825fec3
- [ARM] Prevent constants from iCmp instruction from being hoisted if part of a min(max()) pattern · f7c0e2b8
  Meera Nakrani authored Oct 02, 2020
  f7c0e2b8
- [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV. · 067add7b
  Hsiangkai Wang authored Jul 28, 2020
  067add7b
- Fix limit behavior of dynamic alloca · 9573c9f2
  serge-sans-paille authored Sep 30, 2020
  9573c9f2
- Handle unused variable without asserts · bfd7ee92
  Tres Popp authored Oct 02, 2020
  
  bfd7ee92
- [WebAssembly] Emulate v128.const efficiently · 542523a6
  Thomas Lively authored Oct 02, 2020
  542523a6
- [SVE][CodeGen] Add new EVT/MVT getFixedSizeInBits() functions · b8ce6a67
  David Sherwood authored Oct 01, 2020
  b8ce6a67
- [AArch64] Omit SEH directives for the epilogue if none are needed · afb4e0f2
  Martin Storsjö authored Oct 01, 2020
  afb4e0f2
- [AMDGPU] SIInsertSkips: Tidy block splitting to use splitAt · 2ef9d21e
  Carl Ritson authored Oct 02, 2020
  2ef9d21e
- [PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC. · c4690b00
  Esme-Yi authored Oct 02, 2020
  c4690b00
- [XCOFF] Enable -fdata-sections on AIX · 78a9e62a
  jasonliu authored Oct 01, 2020
  78a9e62a
- [AArch64][SVE] Add lowering for llvm fabs · aab6f7db
  Muhammad Asif Manzoor authored Oct 01, 2020
  aab6f7db
- [AMDGPU] Allow SOP asm mnemonic to differ · caeb13ab
  Stanislav Mekhanoshin authored Oct 01, 2020
  caeb13ab
- [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs · 5402d11b
  Jessica Paquette authored Sep 30, 2020
  5402d11b
- [AArch64][GlobalISel] Use emitTestBit in selection for G_BRCOND · 8e8664e5
  Jessica Paquette authored Oct 01, 2020
  8e8664e5
- [AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP. · 017b8715
  Amara Emerson authored Oct 01, 2020
  017b8715
Oct 01, 2020
- [AArch64][GlobalISel] Make <8 x s8> integer arithmetic ops legal. · e28c5899
  Amara Emerson authored Oct 01, 2020
  
  e28c5899
- [AArch64][GlobalISel] Make <8 x s8> shifts legal and add selection support. · a97e97fa
  Amara Emerson authored Oct 01, 2020
  
  a97e97fa
- Revert "[AArch64][GlobalISel] Make <8 x s8> shifts legal." · 9a2b3bbc
  Amara Emerson authored Oct 01, 2020
  9a2b3bbc
- [AArch64][GlobalISel] Make <8 x s8> shifts legal. · 8071c2f5
  Amara Emerson authored Oct 01, 2020
  
  8071c2f5
- [AArch64][GlobalISel] Merge G_SHL, G_ASHR and G_LSHR legalizer rules together. · 9f6acb13
  Amara Emerson authored Oct 01, 2020
  9f6acb13
- [AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors. · 73457536
  Amara Emerson authored Sep 23, 2020
  73457536
- [AArch64][GlobalISel] Camp oversize v4s64 G_FPEXT operations. · 4c265ce6
  Amara Emerson authored Oct 01, 2020
  
  4c265ce6
- [AArch64] Don't merge sp decrement into later stores when using WinCFI · f4b9dfd9
  Martin Storsjö authored Sep 29, 2020
  f4b9dfd9
- [AArch64] Remove a duplicate call to setHasWinCFI. NFCI. · 51e74e21
  Martin Storsjö authored Oct 01, 2020
  51e74e21
- [ARM] Removed hasSideEffects from signed/unsigned saturates · 48c9e824
  Meera Nakrani authored Oct 01, 2020
  48c9e824
- [AMDGPU] Simplify getNumFlatOffsetBits. NFC. · e20f4592
  Jay Foad authored Oct 01, 2020
  e20f4592
- [AMDGPU] Tiny cleanup in isLegalFLATOffset. NFC. · 866d9b03
  Jay Foad authored Oct 01, 2020
  
  866d9b03
- [NFC][ARM] LowOverheadLoop DEBUG statements · 7e02bc81
  Sam Parker authored Oct 01, 2020
  
  7e02bc81
- [SVE][CodeGen] Lower scalable fp_extend & fp_round operations · fcf70e1e
  Kerry McLaughlin authored Oct 01, 2020
  fcf70e1e
- [ARM][LowOverheadLoops] Adjust Start insertion. · 38f625d0
  Sam Parker authored Oct 01, 2020
  38f625d0
- [SVE][CodeGen] Legalisation of integer -> floating point conversions · 75db7cf7
  Kerry McLaughlin authored Sep 30, 2020
  75db7cf7
- [NFC] Iterate across an explicit list of scalable MVTs when driving setOperationAction. · 8931c3d6
  Paul Walker authored Sep 25, 2020
  8931c3d6
- [ARM][LowOverheadLoops] Iteration count liveness · 6ec5f324
  Sam Parker authored Sep 30, 2020
  6ec5f324
- [ARM][LowOverheadLoops] Start insertion point · 7b90516d
  Sam Parker authored Sep 30, 2020
  7b90516d
- [ARM][LowOverheadLoops] Use iterator for InsertPt. · dfa2c14b
  Sam Parker authored Sep 30, 2020
  dfa2c14b
- [AArch64][GlobalISel] Select all-zero G_BUILD_VECTOR into a zero mov. · da11479f
  Amara Emerson authored Sep 18, 2020
  da11479f
- [AVR] fix interrupt stack pointer restoration · 1fedd90c
  Andrew Dona-Couch authored Oct 01, 2020
  1fedd90c