Commits · f3db8e3c70491442e2747e2dfa8cc3c07b3b40d1 · Roger Ferrer / llvm-epi · GitLab

Apr 02, 2018
- Remove HAVE_DIRENT_H. · f3db8e3c
  Nico Weber authored Apr 02, 2018
  f3db8e3c
- [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16 · b181c731
  Dmitry Preobrazhensky authored Apr 02, 2018
  b181c731
- [profile] Fix value profile runtime merging issues · 95ab7582
  Rong Xu authored Apr 02, 2018
  95ab7582
- [coroutines] Add support for llvm.coro.noop intrinsics · b0316d96
  Gor Nishanov authored Apr 02, 2018
  b0316d96
- [Core] Grab-bag of improvements for Scalar. · 49d80286
  Davide Italiano authored Apr 02, 2018
  49d80286
- Support template template parameters · f4e7e521
  Frederic Riss authored Apr 02, 2018
  f4e7e521
- [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions · 6bad04ec
  Dmitry Preobrazhensky authored Apr 02, 2018
  6bad04ec
- [PPC] Add a test for toc-relative access on ppc64le. · 6bf3fe12
  Sean Fertile authored Apr 02, 2018
  6bf3fe12
- [Hexagon] Clean up some code in HexagonAsmPrinter, NFC · 0831f57a
  Krzysztof Parzyszek authored Apr 02, 2018
  0831f57a
- [SLP] Fix PR36481: vectorize reassociated instructions. · 3decaf42
  Alexey Bataev authored Apr 02, 2018
  3decaf42
- Remove stro(u?)ll() config checks. Those were needed pre-MSVC2013, but we require 2015 nowadays. · 426f0ceb
  Nico Weber authored Apr 02, 2018
  426f0ceb
- Revert r328975, it makes TableGen assert on the bots. · f492f581
  Nico Weber authored Apr 02, 2018
  f492f581
- Remove HAVE_WRITEV that's unused after r255837. · 9f03e9de
  Nico Weber authored Apr 02, 2018
  9f03e9de
- More fixes after r328970. · ae2a14be
  Nico Weber authored Apr 02, 2018
  ae2a14be
- [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions · 32c450ae
  Dmitry Preobrazhensky authored Apr 02, 2018
  32c450ae
- Attempt to heal bots after r328970. · 2eada78a
  Nico Weber authored Apr 02, 2018
  2eada78a
- [X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346 · 92746830
  Lama Saba authored Apr 02, 2018
  92746830
- [llvm-mca] Do not assume that implicit reads cannot be associated with ReadAdvance entries. · 6fd62fef
  Andrea Di Biagio authored Apr 02, 2018
  6fd62fef
- Attempt to fix papertrail-warnings.test on Windows bots. · 62ea0c56
  Nico Weber authored Apr 02, 2018
  62ea0c56
- Assume existence of inttypes.h and stdint.h in DataTypes.h. · dce9a72d
  Nico Weber authored Apr 02, 2018
  dce9a72d
- [PowerPC] fix assertion failure due to missing instruction in P9InstrResources.td · 6d484938
  Hiroshi Inoue authored Apr 02, 2018
  6d484938
- Fix unused variable warning introduced at revision 328910. · d3144ea8
  Andrea Di Biagio authored Apr 02, 2018
  d3144ea8
- [ELF] - cref.s: check that we print symbols from archives. NFCI. · 5b31b6f1
  George Rimar authored Apr 02, 2018
  5b31b6f1
- [test] Exit lldb-dotest in a more Pythonic way. · aa430c01
  Jonas Devlieghere authored Apr 02, 2018
  aa430c01
- [dsymutil] Upstream emitting of papertrail warnings. · 9e3e7a99
  Jonas Devlieghere authored Apr 02, 2018
  9e3e7a99
- Wdocumentation fix. NFCI. · 3f0bda29
  Simon Pilgrim authored Apr 02, 2018
  3f0bda29
- Wdocumentation fixes. NFCI. · 49a5ddfd
  Simon Pilgrim authored Apr 02, 2018
  49a5ddfd
- [X86][Silvermont] Use correct latency and throughput information for divide... · 96729cd6
  Craig Topper authored Apr 02, 2018
  96729cd6
- [X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide. · 6a814904
  Craig Topper authored Apr 02, 2018
  6a814904
- [X86] Correct the throughput for divide instructions in Sandy... · 8104f266
  Craig Topper authored Apr 02, 2018
  8104f266
- [X86] Fix the SchedRW for AVX512 shift instructions. · dc740943
  Craig Topper authored Apr 02, 2018
  dc740943
- [X86] Give the AVX512 VEXTRACT instructions the same SchedRWs as the SSE/AVX versions. · 5fb1dc2d
  Craig Topper authored Apr 02, 2018
  5fb1dc2d
- Remove a few unreferenced config.h defines. · 7a4f647d
  Nico Weber authored Apr 02, 2018
  7a4f647d
- [X86] Add an itinerary to BTR64rr. · caec723a
  Craig Topper authored Apr 02, 2018
  caec723a
- [X86] Make sure all the classes declare in the Haswell scheduler model are prefixed with HW. · 02daec00
  Craig Topper authored Apr 02, 2018
  02daec00
- [X86] Give VINSERTPS the same intinerary as INSERTPS. · c90d906b
  Craig Topper authored Apr 02, 2018
  c90d906b
- Add C API bindings for DIBuilder 'Type' APIs · b7881bbf
  Harlan Haskins authored Apr 02, 2018
  b7881bbf
- [X86] Cleanup ADCX/ADOX instruction definitions. · dc4a6d1e
  Craig Topper authored Apr 01, 2018
  dc4a6d1e
- [Coroutines] Schedule coro-split before asan · 91a4b5af
  Brian Gesiak authored Apr 01, 2018
  91a4b5af
- [AArch64] Reserve x18 register on Fuchsia · 934e5d54
  Petr Hosek authored Apr 01, 2018
  934e5d54