Commits · f40682a930d6812c930f90495933f9e3dfb9fcd3 · Roger Ferrer / llvm-epi · GitLab

Jun 29, 2023
- [RISCV] Remove legacy TA/TU pseudo distinction for unary instructions · 92b5a340
  Philip Reames authored Jun 29, 2023
  92b5a340
- [RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node · 9d22b54d
  Yunze Zhu authored Jun 29, 2023
  9d22b54d
- [RISCV] Do a more complete job of disabling extending loads and truncating... · 1c676e08
  Craig Topper authored Jun 29, 2023
  1c676e08
- [RISCV] Update computeKnownBitsForTargetNode for FPCLASS. · a09a19be
  Jianjian GUAN authored Jun 29, 2023
  a09a19be
- [RISCV] Bump vector crypto to v1.0.0-rc1 · 02f94a65
  4vtomat authored Jun 27, 2023
  02f94a65
Jun 28, 2023
- [RISCV] Add test cases for vmv.v.vs which could be combined · 699e0bed
  Luke Lau authored Jun 20, 2023
  699e0bed
- [RISCV] Add test cases for insert subvector shuffles for fixed vectors · 3e1a7510
  Luke Lau authored Jun 13, 2023
  3e1a7510
- [DAGCombine] Fold (store (insert_elt (load p)) x p) -> (store x) · 742fb8b5
  Luke Lau authored Jun 06, 2023
  742fb8b5
- [RISCV] Add fixed vector insert tests that are pass by value · 9ad29e7b
  Luke Lau authored Jun 28, 2023
  9ad29e7b
Jun 27, 2023
- [RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines. · 6e4be7e1
  Craig Topper authored Jun 27, 2023
  6e4be7e1
- [RISCV] Remove legacy TA/TU pseudo distinction for VID · 65de6b0b
  Philip Reames authored Jun 27, 2023
  65de6b0b
Jun 26, 2023
- Ignore load/store until stack address computation · 02ba5b8c
  Matthias Braun authored Jun 05, 2023
  02ba5b8c
- [RISCV] Regen rvv/fixed-vectors-fmf.ll to avoid spurious test deltas · 237efe7e
  Philip Reames authored Jun 26, 2023
  
  237efe7e
- [RISCV][SelectionDAGBuilder] Fix an implicit scalable TypeSize to fixed size... · 4afa2ab7
  Craig Topper authored Jun 26, 2023
  4afa2ab7
- [SelectionDAG] Improve expansion of wide min/max · bc7f11cc
  Eli Friedman authored May 24, 2023
  bc7f11cc
- [RISCV] Teach doPeepholeMaskedRVV to handle vslide{up,down} · 0e9384a6
  Luke Lau authored Jun 23, 2023
  0e9384a6
- [RISCV] Add test cases for vmerge peephole with vslides · 0d0bfa8a
  Luke Lau authored Jun 23, 2023
  0d0bfa8a
- [RISCV] Properly handle partial writes in isConvertibleToVMV_V_V. · b105b326
  Craig Topper authored Jun 25, 2023
  b105b326
- [RISCV] Add test case for D153490. NFC · 43e57bda
  Craig Topper authored Jun 25, 2023
  
  43e57bda
Jun 24, 2023
- Recommit "[RISCV] Implement support for bf16 truncate/extend on hard FP targets" · 92912499
  Alex Bradbury authored Jun 23, 2023
  92912499
- Revert "[RISCV] Implement support for bf16 truncate/extend on hard FP targets" · 076759f0
  Craig Topper authored Jun 23, 2023
  076759f0
- [RISCV] Implement KCFI operand bundle lowering · 83835e22
  Sami Tolvanen authored Jun 23, 2023
  83835e22
Jun 23, 2023
- Revert "[RISCV] Implement KCFI operand bundle lowering" · e809ebeb
  Sami Tolvanen authored Jun 23, 2023
  e809ebeb
- [RISCV] Implement KCFI operand bundle lowering · 62fa708c
  Sami Tolvanen authored Jun 23, 2023
  62fa708c
- [DAG] Fix and expand fmin/fmax reassociation fold. · 589c940e
  David Green authored Jun 23, 2023
  589c940e
- [RISCV] Implement support for bf16 truncate/extend on hard FP targets · 690b1c84
  Alex Bradbury authored Jun 23, 2023
  690b1c84
Jun 22, 2023
- [RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status. · 08f1aa87
  Craig Topper authored Jun 22, 2023
  08f1aa87
- [RISCV] Strengthen atomic ordering for sequentially consistent stores · 3ea8f252
  Paul Kirth authored Apr 19, 2023
  3ea8f252
Jun 21, 2023
- [RISCV] Custom lower fixed vector undef to scalable undef · 485d2500
  Luke Lau authored Jun 21, 2023
  485d2500
- [RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vector lowreing. · aae155c5
  Craig Topper authored Jun 21, 2023
  aae155c5
- [RISCV] Stop isInterleaveShuffle from producing illegal extract_subvectors. · ddf3f1b3
  Craig Topper authored Jun 21, 2023
  ddf3f1b3
- RISCV: Update test · 6e8911e4
  Matt Arsenault authored Jun 21, 2023
  
  6e8911e4
- RegisterCoalescer: Fix name of pass · 80e2c26d
  Matt Arsenault authored Jun 21, 2023
  80e2c26d
- [RISCV] Add a pass to merge moving parameter registers instructions for Zcmp · c9e08fa6
  WuXinlong authored Jun 21, 2023
  c9e08fa6
Jun 20, 2023
- [RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu · 9ed668ad
  eopXD authored Jun 13, 2023
  9ed668ad
- [3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub · 5510f0b8
  eopXD authored May 24, 2023
  5510f0b8
- [2/3][RISCV][POC] Model vxrm in LLVM intrinsics and machine instructions for... · 7c836512
  eopXD authored May 23, 2023
  7c836512
- [RISCV] Remove mask from vrgatherei16 in lowerVECTOR_INTERLEAVE. · 8680c28a
  Craig Topper authored Jun 20, 2023
  8680c28a
- InlineSpiller: Consider copy bundles when looking for snippet copies · 7dcb9c0f
  Matt Arsenault authored Mar 20, 2023
  7dcb9c0f
Jun 19, 2023
- [RISCV] Match shl (ext v, splat 1) to vector widening add. · 04ed822d
  Jianjian GUAN authored Jun 16, 2023
  04ed822d