Commits · f423f5627caed62aadb02ebecfc464dfb1c99097 · Roger Ferrer / llvm-epi · GitLab

Jul 06, 2015
- Change the last few internal StringRef triples into Triple objects. · f423f562
  Daniel Sanders authored Jul 06, 2015
  f423f562
Jun 02, 2015
- [AArch64] Add v8.1a atomic instructions · 5f6f60d9
  Vladimir Sukharev authored Jun 02, 2015
  5f6f60d9
May 13, 2015
- MC: Modernize MCOperand API naming. NFC. · e9119e41
  Jim Grosbach authored May 13, 2015
  e9119e41
Apr 16, 2015
- [AArch64] Add v8.1a "Limited Ordering Regions" extension · d49cb8fd
  Vladimir Sukharev authored Apr 16, 2015
  d49cb8fd
- [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget features. · a98f6897
  Vladimir Sukharev authored Apr 16, 2015
  a98f6897
Jan 18, 2015
- unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizer · 186db431
  David Blaikie authored Jan 18, 2015
  186db431
Nov 12, 2014
- Pass an ArrayRef to MCDisassembler::getInstruction. · 7fc5b874
  Rafael Espindola authored Nov 12, 2014
  7fc5b874
Nov 10, 2014
- Misc style fixes. NFC. · 4aa6bea7
  Rafael Espindola authored Nov 10, 2014
  4aa6bea7
Oct 01, 2014
- [AArch64] Allow access to all system registers with MRS/MSR instructions. · e493f177
  Tom Coxon authored Oct 01, 2014
  e493f177
Sep 30, 2014
- [AArch64] Remove unnecessary whitespace. (Test commit) · 2c13e717
  Tom Coxon authored Sep 30, 2014
  2c13e717
Sep 02, 2014
- Fix left shifts of negative integers in AArch64 InstPrinter/Disassembler · 729b12ed
  Alexey Samsonov authored Sep 02, 2014
  729b12ed
Jul 25, 2014
- Run sort_includes.py on the AArch64 backend. · 1f8930e3
  Benjamin Kramer authored Jul 25, 2014
  1f8930e3
Jul 23, 2014
- AArch64: remove "arm64_be" support in favour of "aarch64_be". · 35910d7f
  Tim Northover authored Jul 23, 2014
  35910d7f
May 24, 2014
- AArch64/ARM64: move ARM64 into AArch64's place · 3b0846e8
  Tim Northover authored May 24, 2014
  3b0846e8
- AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. · cc08e1fe
  Tim Northover authored May 24, 2014
  cc08e1fe
May 22, 2014
- ARM64: model pre/post-indexed operations properly. · 4a3ab28a
  Tim Northover authored May 22, 2014
  4a3ab28a
- ARM64: separate load/store operands to simplify assembler · c350acfd
  Tim Northover authored May 22, 2014
  c350acfd
May 19, 2014
- [ARM64] Split tbz/tbnz into W/X register variant · c3b931d0
  Bradley Smith authored May 19, 2014
  c3b931d0
May 15, 2014
- [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted · e0483f9c
  Bradley Smith authored May 15, 2014
  e0483f9c
May 06, 2014
- AArch64/ARM64: implement diagnosis of unpredictable loads & stores · 618850b6
  Tim Northover authored May 06, 2014
  618850b6
May 02, 2014
- ARM64: refactor NEON post-indexed loads & stores (MC). · 523b5a43
  Tim Northover authored May 02, 2014
  523b5a43
May 01, 2014
- [ARM64] Conditionalize CPU specific system registers on subtarget features · f57d5ca2
  Bradley Smith authored May 01, 2014
  f57d5ca2
Apr 30, 2014
- AArch64/ARM64: expunge CPSR from the sources · d53a6713
  Tim Northover authored Apr 30, 2014
  d53a6713
Apr 24, 2014
- AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands · 79ec0192
  Tim Northover authored Apr 24, 2014
  79ec0192
Apr 23, 2014
- [ARM64] Add a big endian version of the ARM64 target machine, and update all users. · 650cb570
  James Molloy authored Apr 23, 2014
  650cb570
Apr 22, 2014
- [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE · 84e68b29
  Chandler Carruth authored Apr 22, 2014
  84e68b29
- [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some · d174b72a
  Chandler Carruth authored Apr 22, 2014
  d174b72a
Apr 21, 2014
- ARM64: Extended addressing mode source reg is 64-bit. · 9d205d42
  Jim Grosbach authored Apr 21, 2014
  9d205d42
Apr 15, 2014
- [MC] Require an MCContext when constructing an MCDisassembler. · a1bc0f56
  Lang Hames authored Apr 15, 2014
  a1bc0f56
Apr 12, 2014
- Make helper static and place random global into the llvm namespace. · 30120c06
  Benjamin Kramer authored Apr 12, 2014
  30120c06
Apr 11, 2014
- Remove redundant symbolization support from MCDisassembler interface. · 95400e22
  Lang Hames authored Apr 11, 2014
  95400e22
Apr 09, 2014
- [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. · a2308f47
  Bradley Smith authored Apr 09, 2014
  a2308f47
- [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. · a19b7e83
  Bradley Smith authored Apr 09, 2014
  a19b7e83
- [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. · af2710c9
  Bradley Smith authored Apr 09, 2014
  af2710c9
- [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. · eb4ca04d
  Bradley Smith authored Apr 09, 2014
  eb4ca04d
- [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. · 4925be9b
  Bradley Smith authored Apr 09, 2014
  4925be9b
- [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to... · 08c391c1
  Bradley Smith authored Apr 09, 2014
  08c391c1
- [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64.... · 2ba17a4a
  Bradley Smith authored Apr 09, 2014
  2ba17a4a
- [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also... · 8c0b88c9
  Bradley Smith authored Apr 09, 2014
  8c0b88c9
- [ARM64] STRHro and STRBro were not being decoded at all. · 35cadc58
  Bradley Smith authored Apr 09, 2014
  35cadc58