Commits · f445a56b61c2606378ab37c8635dcb1a3f45db8e · Roger Ferrer / llvm-epi · GitLab

Oct 16, 2014
- Test commit access: remove extra new line at the end of file · f445a56b
  Vasileios Kalintiris authored Oct 16, 2014
  f445a56b
- R600: Remove dead function · f1b34cf6
  Matt Arsenault authored Oct 16, 2014
  f1b34cf6
- [AVX512] Add DQ subvector inserts · 4285c1f8
  Adam Nemet authored Oct 15, 2014
  4285c1f8
- [AVX512] Two new attributes in X86VectorVTInfo for subvector insert · 449b3f09
  Adam Nemet authored Oct 15, 2014
  449b3f09
- [AVX512] Rename arg from Opcode32/64 to Opcode128/256 in vinsert_for_size · b1c3ef4b
  Adam Nemet authored Oct 15, 2014
  b1c3ef4b
- R600: Remove unnecessary part of computeKnownBitsForTargetNode · 20893b36
  Matt Arsenault authored Oct 15, 2014
  20893b36
- Move variable down to use · 6de7af42
  Matt Arsenault authored Oct 15, 2014
  6de7af42
Oct 15, 2014
- R600/SI: Fix bug where immediates were being used in DS addr operands · c8d7920a
  Tom Stellard authored Oct 15, 2014
  c8d7920a
- Wrong attribute. LLVM_ATTRIBUTE_UNUSED not LLVM_ATTRIBUTE_USED · a0022964
  Sid Manning authored Oct 15, 2014
  a0022964
- Wrong attribute. LLVM_ATTRIBUTE_USED not LLVM_ATTRIBUTE_UNUSED · 2ceaeb6b
  Sid Manning authored Oct 15, 2014
  2ceaeb6b
- Add LLVM_ATTRIBUTE_UNUSED to function currently just used in an assert · 74cd020f
  Sid Manning authored Oct 15, 2014
  74cd020f
- Reapply "[FastISel][AArch64] Add custom lowering for GEPs." · f82c987a
  Juergen Ributzka authored Oct 15, 2014
  f82c987a
- [FastISel][AArch64] Factor out add with immediate emission into a helper function. NFC. · 6780f0f7
  Juergen Ributzka authored Oct 15, 2014
  6780f0f7
- Enable the instruction printer in HexagonMCTargetDesc · 12cd21aa
  Sid Manning authored Oct 15, 2014
  12cd21aa
- R600/SI: Also try to use 0 base for misaligned 8-byte DS loads. · 1a74aff8
  Matt Arsenault authored Oct 15, 2014
  1a74aff8
- R600: Fix miscompiles when BFE has multiple uses · 7b68fdf3
  Matt Arsenault authored Oct 15, 2014
  7b68fdf3
- Simplify handling of --noexecstack by using getNonexecutableStackSection. · 7b61ddfa
  Rafael Espindola authored Oct 15, 2014
  7b61ddfa
- Move getNonexecutableStackSection up to the base ELF class. · ad33dd29
  Rafael Espindola authored Oct 15, 2014
  ad33dd29
- R600: Use existing variable · f179420c
  Matt Arsenault authored Oct 15, 2014
  f179420c
- R600: Remove outdated comment · 7acfddf1
  Matt Arsenault authored Oct 15, 2014
  7acfddf1
- Revert "[FastISel][AArch64] Add custom lowering for GEPs." · 42379d4c
  Juergen Ributzka authored Oct 15, 2014
  42379d4c
- ARM: drop check for triple that's no longer used. · e9ff4c29
  Tim Northover authored Oct 15, 2014
  e9ff4c29
- Remove unused variable. · 7396cc99
  Eric Christopher authored Oct 15, 2014
  7396cc99
- [AArch64] Wrong CC access in CSINC-conditional branch sequence · 5d26d40f
  Gerolf Hoflehner authored Oct 14, 2014
  5d26d40f
- [AAarch64] Optimize CSINC-branch sequence · a4c96d02
  Gerolf Hoflehner authored Oct 14, 2014
  a4c96d02
- [X86][SSE] pslldq/psrldq shuffle mask decodes · a798e9ff
  Simon Pilgrim authored Oct 14, 2014
  a798e9ff
- ARM: remove ARM/Thumb distinction for preferred alignment. · cf6ce0c8
  Tim Northover authored Oct 14, 2014
  cf6ce0c8
- ARM: allow misaligned local variables in Thumb1 mode. · 9a4c043d
  Tim Northover authored Oct 14, 2014
  9a4c043d
Oct 14, 2014
- [FastISel][AArch64] Add custom lowering for GEPs. · 4dfd590e
  Juergen Ributzka authored Oct 14, 2014
  4dfd590e
- [x86 asm] allow fwait alias in both At&t and Intel modes (PR21208) · f6aafeee
  Hans Wennborg authored Oct 14, 2014
  f6aafeee
- ARM: set preferred aggregate alignment to 32 universally. · aa09ac6e
  Tim Northover authored Oct 14, 2014
  aa09ac6e
- [FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved. · cd11a280
  Juergen Ributzka authored Oct 14, 2014
  cd11a280
- Reapply "R600: Add new intrinsic to read work dimensions" · e5121f3c
  Jan Vesely authored Oct 14, 2014
  e5121f3c
- Revert "R600: Add new intrinsic to read work dimensions" · db3f0a24
  Rafael Espindola authored Oct 14, 2014
  db3f0a24
- R600: Add new intrinsic to read work dimensions · 86187d23
  Jan Vesely authored Oct 14, 2014
  86187d23
- R600: FMA is VecALU only instruction · df196963
  Jan Vesely authored Oct 14, 2014
  df196963
- Finish getting Mips fast-isel to match up with AArch64 fast-isel · d4ea29e6
  Reed Kotler authored Oct 14, 2014
  d4ea29e6
- R600/SI: Use DS offsets for constant addresses · e775f5fe
  Matt Arsenault authored Oct 14, 2014
  e775f5fe
- [AVX512] Extended avx512_binop_rm to DQ/VL subsets. · 1a77f666
  Robert Khasanov authored Oct 14, 2014
  1a77f666
- [AVX512] Extended avx512_binop_rm to BW/VL subsets. · 545d1b77
  Robert Khasanov authored Oct 14, 2014
  545d1b77