Commits · f4572249d78d13b16cb287500a3bcd226ececb31 · Roger Ferrer / llvm-epi · GitLab

Jul 10, 2019
- Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe... · f4572249
  Michael Berg authored Jul 10, 2019
  f4572249
- [LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map. · 58a37754
  Alina Sbirlea authored Jul 10, 2019
  58a37754
- [X86] Regenerate tests. NFCI. · 5a6d40be
  Simon Pilgrim authored Jul 10, 2019
  5a6d40be
- [X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC · ab5a30ac
  Craig Topper authored Jul 10, 2019
  ab5a30ac
- [TargetLowering] support BlockAddress as "i" inline asm constraint · 8728e457
  Nick Desaulniers authored Jul 10, 2019
  8728e457
- [NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests · 20b45a61
  Roman Lebedev authored Jul 10, 2019
  20b45a61
- MC: AArch64: Add support for pg_hi21_nc relocation specifier. · 893f8d71
  Peter Collingbourne authored Jul 10, 2019
  893f8d71
- [CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451) · 5eb6ba06
  Vedant Kumar authored Jul 10, 2019
  5eb6ba06
- GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM · 6ce1b4fe
  Matt Arsenault authored Jul 10, 2019
  6ce1b4fe
- GlobalISel: Define the full family of FP min/max instructions · e595a2c9
  Matt Arsenault authored Jul 10, 2019
  e595a2c9
- AMDGPU: Serialize mode from MachineFunctionInfo · 58426a37
  Matt Arsenault authored Jul 10, 2019
  58426a37
- [NFC][InstCombine] Redundant masking before left-shift (PR42563) · 1c51073a
  Roman Lebedev authored Jul 10, 2019
  1c51073a
- [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32 · bba37e89
  Jay Foad authored Jul 10, 2019
  bba37e89
- [InstCombine] pow(C,x) -> exp2(log2(C)*x) · 0735cc19
  David Bolvansky authored Jul 10, 2019
  0735cc19
- [InferFunctionAttrs] add/adjust tests for dereferenceable; NFC · 9cd82a4f
  Sanjay Patel authored Jul 10, 2019
  9cd82a4f
- [MIPS GlobalISel] Select float and double phi · 7d0778ea
  Petar Avramovic authored Jul 10, 2019
  7d0778ea
- [MIPS GlobalISel] Select float and double load and store · 7b31491a
  Petar Avramovic authored Jul 10, 2019
  7b31491a
- [ELF] Loose a condition for relocation with a symbol · fb163b4b
  Nikola Prica authored Jul 10, 2019
  fb163b4b
- [X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support · 6a585839
  Simon Pilgrim authored Jul 10, 2019
  6a585839
- [SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with one unique successor · d000f8b6
  Serguei Katkov authored Jul 10, 2019
  d000f8b6
- [ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present · ed143c5d
  Mikhail Maltsev authored Jul 10, 2019
  ed143c5d
- [test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries. · 4e09ef03
  George Rimar authored Jul 10, 2019
  4e09ef03
- [SimpleLoopUnswitch] Add a test case exposing a bug · 97f19f3a
  Serguei Katkov authored Jul 10, 2019
  97f19f3a
- AMDGPU/GlobalISel: Add support for wide loads >= 256-bits · d0ba79fe
  Tom Stellard authored Jul 10, 2019
  d0ba79fe
- GlobalISel: Implement lower for G_FCOPYSIGN · b1843e13
  Matt Arsenault authored Jul 09, 2019
  b1843e13
- AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR · 3f1a3454
  Matt Arsenault authored Jul 09, 2019
  3f1a3454
- [AMDGPU] gfx908 v_pk_fmac_f16 support · 1e9eae95
  Stanislav Mekhanoshin authored Jul 09, 2019
  1e9eae95
- GlobalISel: Combine unmerge of merge with intermediate cast · 14a44951
  Matt Arsenault authored Jul 09, 2019
  14a44951
Jul 09, 2019
- [llvm-objdump] Keep warning for --disassemble-functions in correct order. · c5f8aa8b
  Yuanfang Chen authored Jul 09, 2019
  c5f8aa8b
- [AMDGPU] gfx908 mAI instructions, MC part · 50d7f464
  Stanislav Mekhanoshin authored Jul 09, 2019
  50d7f464
- hwasan: Improve precision of checks using short granule tags. · 1366262b
  Peter Collingbourne authored Jul 09, 2019
  1366262b
- [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into... · 84a1f073
  Craig Topper authored Jul 09, 2019
  84a1f073
- [AMDGPU] gfx908 register file changes · 9e77d0c6
  Stanislav Mekhanoshin authored Jul 09, 2019
  9e77d0c6
- [PoisonCheker] Support for out of bounds operands on shifts + insert/extractelement · 3dbd7e98
  Philip Reames authored Jul 09, 2019
  3dbd7e98
- Boilerplate for producing XCOFF object files from the PowerPC backend. · f09d54ed
  Sean Fertile authored Jul 09, 2019
  f09d54ed
- [PoisonChecking] Add validation rules for "exact" on sdiv/udiv · 3b38b925
  Philip Reames authored Jul 09, 2019
  3b38b925
- [ThinLTO] only emit used or referenced CFI records to index · 6a4c2e4f
  Bob Haarman authored Jul 09, 2019
  6a4c2e4f
- Add a transform pass to make the executable semantics of poison explicit in the IR · f47a313e
  Philip Reames authored Jul 09, 2019
  f47a313e
- [AMDGPU] gfx908 target · 22b2c3d6
  Stanislav Mekhanoshin authored Jul 09, 2019
  22b2c3d6
- [Object][XCOFF] Add support for 64-bit file header and section header dumping. · 837ae69f
  Sean Fertile authored Jul 09, 2019
  837ae69f