Commits · f4c5cadbcbb41f13cff0905449cfff4aef6a083c · Roger Ferrer / llvm-epi · GitLab

Sep 21, 2020
- [ARM] Select f32 constants with vmov.f16 · f4c5cadb
  David Green authored Sep 21, 2020
  f4c5cadb
- [NFC][ARM] More tail predication tests. · 13c73632
  Sam Parker authored Sep 21, 2020
  13c73632
- [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder · 53d238a9
  Lucas Prates authored Sep 17, 2020
  53d238a9
- [PowerPC] Pass nofpexcept flag to custom lowered constrained ops · 1d782c29
  Qiu Chaofan authored Sep 21, 2020
  1d782c29
- [XRay] Change mips to use version 2 sled (PC-relative address) · d0648568
  Fangrui Song authored Sep 19, 2020
  d0648568
Sep 20, 2020
- [X86] Make reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore work... · a74b1fab
  Craig Topper authored Sep 20, 2020
  a74b1fab
- [X86] Pre-commit test cases for D87863. NFC · c89b3af0
  Craig Topper authored Sep 20, 2020
  
  c89b3af0
- [X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from... · 4e8c0281
  Craig Topper authored Sep 20, 2020
  4e8c0281
- [X86] Add 32-bit command lines to masked_store.ll and masked_load.ll · 9b1c98c0
  Craig Topper authored Sep 20, 2020
  
  9b1c98c0
- [ARM] Constant fold VMOVrh · 29bd8ea1
  David Green authored Sep 20, 2020
  29bd8ea1
- [X86][SSE] Fold EXTEND_VECTOR_INREG(EXTRACT_SUBVECTOR(EXTEND(X),0)) -> EXTEND_VECTOR_INREG(X) · 0bfeede6
  Simon Pilgrim authored Sep 20, 2020
  
  0bfeede6
- [X86][SSE] Fold SIGN_EXTEND(SIGN_EXTEND_VECTOR_INREG(X)) -> SIGN_EXTEND_VECTOR_INREG(X) · bb0078e5
  Simon Pilgrim authored Sep 20, 2020
  bb0078e5
- [X86][SSE] Fold EXTEND_VECTOR_INREG(EXTEND_VECTOR_INREG(X)) -> EXTEND_VECTOR_INREG(X) · 15c83060
  Simon Pilgrim authored Sep 20, 2020
  15c83060
- [X86][SSE] Enable ZERO_EXTEND_VECTOR_INREG shuffle combining on SSE41 targets. · a0c8793c
  Simon Pilgrim authored Sep 20, 2020
  a0c8793c
Sep 19, 2020
- [AArch64][GlobalISel] Add legalization and selection support for <4 x s16> G_SHL. · 5a50f8b3
  Amara Emerson authored Sep 18, 2020
  
  5a50f8b3
- [X86] Fix copy paste mistake in @ccnp flag. · 58ecbbcd
  Craig Topper authored Sep 18, 2020
  58ecbbcd
- [X86] Invert the compares in inline-asm-flag-output.ll so that the setcc... · 5e6baf78
  Craig Topper authored Sep 18, 2020
  5e6baf78
- Temporarily Revert "RegAllocFast: Rewrite and improve" · dbd53a1f
  Eric Christopher authored Sep 18, 2020
  dbd53a1f
- [AArch64][GlobalISel] Add tests for pre-existing selection support for <4 x... · cce24bb3
  Amara Emerson authored Sep 18, 2020
  cce24bb3
- [AArch64][GlobalISel] Legalize arithmetic ops for <4 x s16> · 269bcc39
  Amara Emerson authored Sep 18, 2020
  
  269bcc39
- [GlobalISel] Add lowering support for G_ABS and use for AArch64. · 5d34d7f1
  Amara Emerson authored Sep 18, 2020
  5d34d7f1
- [PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang · 37e7673c
  Amy Kwan authored Sep 18, 2020
  37e7673c
Sep 18, 2020
- [COFF] Move per-global .drective emission from AsmPrinter to TLOFCOFF · 9932561b
  Reid Kleckner authored Sep 18, 2020
  9932561b
- [X86][AVX] lowerBuildVectorAsBroadcast - improve BROADCASTM lowering on non-VLX targets · 4ebd3072
  Simon Pilgrim authored Sep 18, 2020
  4ebd3072
- PR47468: Fix findPHICopyInsertPoint, so that copies aren't incorrectly... · f7a53d82
  James Y Knight authored Sep 17, 2020
  f7a53d82
- [X86][AVX] Add missing non AVX512VL broadcastm test coverage · ecba9d79
  Simon Pilgrim authored Sep 18, 2020
  
  ecba9d79
- RegAllocFast: Rewrite and improve · c8757ff3
  Matt Arsenault authored Sep 14, 2020
  c8757ff3
- Reapply "RegAllocFast: Record internal state based on register units" · 870fd53e
  Matt Arsenault authored Sep 15, 2020
  870fd53e
- AMDGPU: Don't sometimes allow instructions before lowered si_end_cf · 0576f436
  Matt Arsenault authored Sep 10, 2020
  0576f436
- [AArch64][GlobalISel] Make <8 x s8> of G_BUILD_VECTOR legal. · 615695de
  Amara Emerson authored Sep 18, 2020
  
  615695de
- [X86][AVX] lowerBuildVectorAsBroadcast - improve i64 BROADCASTM lowering on 32-bit targets · ceadd98c
  Simon Pilgrim authored Sep 18, 2020
  ceadd98c
- [X86][AVX] Add missing i686 broadcastm test coverage · 81dce71a
  Simon Pilgrim authored Sep 18, 2020
  
  81dce71a
- Revert "[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel." · 27df1652
  Matt Arsenault authored Sep 17, 2020
  27df1652
- [AMDGPU] Set DS alignment requirements to be more strict · ae36c02a
  Mirko Brkusanin authored Sep 18, 2020
  ae36c02a
- Recommit "[DSE] Switch to MemorySSA-backed DSE by default." · 9d172c8e
  Florian Hahn authored Sep 18, 2020
  9d172c8e
- AArch64: make sure jump table entries can reach entire image · 2afe4bec
  Tim Northover authored Sep 08, 2020
  2afe4bec
- [AArch64] Add tests for zext pattern match with AssertZext/AssertSext operand, NFC · 8f09cec8
  Andrew Wei authored Sep 18, 2020
  
  8f09cec8
- [X86] Add some demanded bits test cases for PDEP with constant mask · fb92f863
  Craig Topper authored Sep 17, 2020
  fb92f863
- [AArch64] Emit zext move when the source of the zext is AssertZext or AssertSext · 992698cf
  Andrew Wei authored Sep 18, 2020
  992698cf
- [AArch64][GlobalISel] Make G_STORE <8 x s8> legal. · f5898f8c
  Amara Emerson authored Sep 17, 2020
  
  f5898f8c