Commits · f4ef79306cee2b5866aff681174f16b816810c4a · Roger Ferrer / llvm-epi · GitLab

Jan 04, 2022
- [AVR] Optimize int8 arithmetic right shift 6 bits · f4ef7930
  Ben Shi authored Jan 04, 2022
  f4ef7930
- [M68k][NFC] Fix unused argument warnings in M68kInstrArithmetic.td · c64ffa22
  Jim Lin authored Jan 04, 2022
  
  c64ffa22
- Revert "[AVR] Optimize int8 arithmetic right shift 6 bits" · 9fb4e79d
  Ben Shi authored Jan 04, 2022
  9fb4e79d
- [AVR] Optimize int8 arithmetic right shift 6 bits · 57232613
  Ben Shi authored Jan 04, 2022
  57232613
- [M68k][NFC] Fix typo in comment. PCD->PCI. · 8b014ad7
  Jim Lin authored Jan 04, 2022
  
  8b014ad7
- [M68k][NFC] Fix file header · 6bf22ae4
  Jim Lin authored Jan 04, 2022
  6bf22ae4
Jan 03, 2022
- [ValueTracking][SelectionDAG] Rename ComputeMinSignedBits->ComputeMaxSignificantBits. NFC · cbcbbd6a
  Craig Topper authored Jan 03, 2022
  cbcbbd6a
- Revert "[llvm] Remove redundant member initialization (NFC)" · e5947760
  Kazu Hirata authored Jan 03, 2022
  e5947760
- [X86] Improve selection of the mov instruction in FrameLowering · a390c990
  Erik Desjardins authored Jan 03, 2022
  a390c990
- [AMDGPU] Use ComputeMinSignedBits and KnownBits::countMaxActiveBits to simplify some code. NFC · 361216f3
  Craig Topper authored Jan 03, 2022
  361216f3
- [ARM][AArch64] Introduce Armv9.3-A · cd7f621a
  Lucas Prates authored Sep 02, 2021
  cd7f621a
- [AArch64] Adding "armv8.8-a" BC instruction. · 8c1e520c
  Simon Tatham authored Feb 11, 2021
  8c1e520c
- [RISCV] Fix the code alignment for GroupFloatVectors. NFC · d38637a0
  Jim Lin authored Jan 03, 2022
  d38637a0
- [RISCV][VP] Add RVV codegen for [nX]vXi1 vp.select · 55271393
  Victor Perez authored Jan 02, 2022
  55271393
- [RISCV] Prune more unnecessary vector pseudo instructions. NFC · bc091e08
  Craig Topper authored Jan 02, 2022
  bc091e08
Jan 02, 2022
- Remove redundant void arguments (NFC) · 7e163afd
  Kazu Hirata authored Jan 02, 2022
  7e163afd
- [Target] Remove unused forward declarations (NFC) · 41bfac6a
  Kazu Hirata authored Jan 02, 2022
  
  41bfac6a
- [AArch64] Remove unused constant NeonBitsPerVector (NFC) · 3f7fd50c
  Kazu Hirata authored Jan 01, 2022
  
  3f7fd50c
- [RISCV] Prune unnecessary vector pseudo instructions. NFC · 4602f416
  Craig Topper authored Jan 01, 2022
  4602f416
- [llvm] Remove redundant member initialization (NFC) · fd480888
  Kazu Hirata authored Jan 01, 2022
  fd480888
Jan 01, 2022
- [ARM] Verify addressing immediates · 319e7759
  David Green authored Jan 01, 2022
  319e7759
- [llvm] Use the default constructor for SDValue (NFC) · 69ccc961
  Kazu Hirata authored Jan 01, 2022
  
  69ccc961
- [Target] Use range-based for loops (NFC) · dd2ad7fa
  Kazu Hirata authored Jan 01, 2022
  
  dd2ad7fa
- [Aarch64] Remove redundant declaration initializeSVEIntrinsicOptsPass (NFC) · f1d56295
  Kazu Hirata authored Jan 01, 2022
  f1d56295
- [AMDGPU] Remove unused declarations fold_exp* and fold_log* (NFC) · bc360fd8
  Kazu Hirata authored Dec 31, 2021
  
  bc360fd8
- [AMDGPU] Remove replaceWithNative (NFC) · 5c4b9ea4
  Kazu Hirata authored Dec 31, 2021
  5c4b9ea4
- [X86] Remove unused declaration getTileStoreShape (NFC) · bfc8f76e
  Kazu Hirata authored Dec 31, 2021
  
  bfc8f76e
- [Hexagon] Use range-based for loops (NFC) · f8f5f1b3
  Kazu Hirata authored Dec 31, 2021
  
  f8f5f1b3
Dec 31, 2021
- [ARM] Introduce an empty "armv8.8-a" architecture. · d50072f7
  Simon Tatham authored Feb 11, 2021
  d50072f7
- [NFC][SVE] Minor reorder of some AArch64ISD nodes and ISel patterns. · b8db4425
  Paul Walker authored Dec 24, 2021
  
  b8db4425
- [MIPS] Add -mfix4300 flag to enable vr4300 mulmul bugfix pass · 2edcde00
  Random authored Dec 27, 2021
  2edcde00
- [RISCV] Use MxListW instead of MxList[0-5]. NFC · 6f45fe98
  Craig Topper authored Dec 31, 2021
  6f45fe98
- [RISCV] Use defvar to simplify some code. NFC · 8811a87e
  Craig Topper authored Dec 30, 2021
  8811a87e
- [RISCV] Use constant pool for large integers · 41454ab2
  Pengcheng Wang authored Dec 31, 2021
  41454ab2
- [RISCV] Fix incorrect cases of vmv.s.f in the VSETVLI insert pass. · 05f82dc8
  Jianjian GUAN authored Dec 31, 2021
  05f82dc8
Dec 30, 2021
- [Hexagon] Generate HVX/FP arithmetic instructions · db83e3e5
  Krzysztof Parzyszek authored Dec 30, 2021
  db83e3e5
- [Hexagon] Generate HVX/FP compare instructions · 9e6afbed
  Krzysztof Parzyszek authored Dec 30, 2021
  9e6afbed
- [RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics. · 15787ccd
  Craig Topper authored Dec 30, 2021
  15787ccd
- [Hexagon] Explicitly use integer types when rescaling a mask · e107374e
  Krzysztof Parzyszek authored Dec 12, 2020
  
  e107374e
- [Hexagon] Handle HVX/FP {masked,wide} loads/stores · eb574259
  Krzysztof Parzyszek authored Dec 30, 2021
  eb574259