Commits · f5ca255d18359bb9fc3c2ddd54b0ed2ee2bdc0a6 · Roger Ferrer / llvm-epi · GitLab

May 08, 2017
- [ARM][NEON] Add support for ISD::ABS lowering · f5ca255d
  Simon Pilgrim authored May 08, 2017
  f5ca255d
- [ARM] Clear the constant pool cache on explicit .ltorg directives · fd4c158a
  Martin Storsjö authored May 08, 2017
  fd4c158a
- [AARCH64][NEON] Add support for ISD::ABS lowering · 7a28a3ac
  Simon Pilgrim authored May 08, 2017
  7a28a3ac
- [GlobalISel][X86] G_GEP selection support. · 810c6257
  Igor Breger authored May 08, 2017
  810c6257
- [GlobalISel][X86] G_MUL legalizer/selector support. · 605b965a
  Igor Breger authored May 08, 2017
  605b965a
- [XRay] Custom event logging intrinsic · 9bcaed86
  Dean Michael Berris authored May 08, 2017
  9bcaed86
May 07, 2017
- [X86][AVX1] Improve 256-bit vector costs for integer unary intrinsics. · 2d1c6d6e
  Simon Pilgrim authored May 07, 2017
  2d1c6d6e
May 06, 2017
- [X86][AVX512] Relax assertion and just exit combine for unsupported types (PR32907) · 33f7397c
  Simon Pilgrim authored May 06, 2017
  33f7397c
- [X86][AVX512] Move v2i64/v4i64 VPABS lowering to tablegen · fea153f3
  Simon Pilgrim authored May 06, 2017
  fea153f3
- [X86] Reduce code for setting operations actions by merging into loops across... · f15a2f4d
  Simon Pilgrim authored May 06, 2017
  f15a2f4d
- [NVPTX] Add support for ISD::ABS lowering · 98f1d026
  Simon Pilgrim authored May 06, 2017
  98f1d026
- [X86][SSE] Break register dependencies on v16i8/v8i16 BUILD_VECTOR on SSE41 · 781cb101
  Simon Pilgrim authored May 06, 2017
  781cb101
- [RegisterBankInfo] Uniquely allocate instruction mapping. · 245994d9
  Quentin Colombet authored May 05, 2017
  245994d9
- [Hexagon] Disable predicated calls by default · ee93e009
  Krzysztof Parzyszek authored May 05, 2017
  ee93e009
- [Hexagon] Remove C6 and C7 as separate registers · e2603328
  Krzysztof Parzyszek authored May 05, 2017
  e2603328
- [RDF] Remove covered parts of reached uses for phi and use in same block · d0c71ef8
  Krzysztof Parzyszek authored May 05, 2017
  d0c71ef8
- ARM: Compute MaxCallFrame size early · 4682ac6c
  Matthias Braun authored May 05, 2017
  4682ac6c
May 05, 2017
- [AMDGPU] In the new waitcnt insertion pass, use getHeader · 5e73b04b
  Kannan Narayanan authored May 05, 2017
  5e73b04b
- [X86] Use SDValue::getConstantOperandVal helper. NFCI. · 430a335b
  Simon Pilgrim authored May 05, 2017
  430a335b
- AMDGPU/AMDHSA: Set COMPUTE_PGM_RSRC2:LDS_SIZE to 0 · 6ccb076a
  Konstantin Zhuravlyov authored May 05, 2017
  6ccb076a
- [bpf] fix a bug which causes incorrect big endian reloc fixup · 7bab73b1
  Alexei Starovoitov authored May 05, 2017
  7bab73b1
- [KnownBits] Add wrapper methods for setting and clear all bits in the... · f0aeee01
  Craig Topper authored May 05, 2017
  f0aeee01
- [AArch64] Remove AArch64AddressTypePromotion pass · 94d42533
  Jun Bum Lim authored May 05, 2017
  94d42533
- [X86][AVX512] Improve support and testing for CTLZ of 512-bit vectors without CDI · ac3c4b6d
  Simon Pilgrim authored May 05, 2017
  ac3c4b6d
- [X86] Remove duplicate operation actions. NFCI. · e9c5d7b7
  Simon Pilgrim authored May 05, 2017
  e9c5d7b7
- [X86][AVX512CDI] Move v2i64/v4i64 and v4i32/v8i32 VPLZCNT lowering to tablegen · c89aa0be
  Simon Pilgrim authored May 05, 2017
  c89aa0be
- Remove unused variable · 73b88d51
  Simon Pilgrim authored May 05, 2017
  73b88d51
- [ARM] Add support for ORR and ORN instruction substitutions · 1b74f8c5
  John Brawn authored May 05, 2017
  1b74f8c5
- [X86][AVX] Add LowerIntUnary helpers to split unary vector ops in half. NFCI. · 1d47a15d
  Simon Pilgrim authored May 05, 2017
  1d47a15d
- [X86] Remove unused code from X86 optimize LEAs. NFC. · 807ca72e
  Andrew Ng authored May 05, 2017
  807ca72e
- Initialize new member X86Operand::FrontendSize in all codepaths. · 07a17719
  Daniel Jasper authored May 05, 2017
  07a17719
- AMDGPU: GFX9 GS and HS shaders always have the scratch wave offset in SGPR5 · 584d2c05
  Marek Olsak authored May 04, 2017
  584d2c05
May 04, 2017
- Strip trailing whitespace. NFCI. · 11a1637a
  Simon Pilgrim authored May 04, 2017
  11a1637a
- [PPC] When restoring R30 (PIC base pointer), mark it as <def> · 038a0546
  Krzysztof Parzyszek authored May 04, 2017
  038a0546
- [ms-inline-asm] Use the frontend size only for ambiguous instructions · 6d2ea6ec
  Reid Kleckner authored May 04, 2017
  6d2ea6ec
- [SystemZ] Make copyPhysReg() add impl-use operands of super reg. · 4fd15626
  Jonas Paulsson authored May 04, 2017
  4fd15626
- [mips][XRay] Use the base version of emitXRayTable · 080d478b
  Simon Dardis authored May 04, 2017
  080d478b
- [X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32. · 70583606
  Igor Breger authored May 04, 2017
  70583606
- [ARM] ACLE Chapter 9 intrinsics · df337704
  Sam Parker authored May 04, 2017
  df337704
- [X86] Disabling PLT in Regcall CC Functions · 51de0330
  Oren Ben Simhon authored May 04, 2017
  51de0330