Commits · f6651d4d9438e185ae92c55978c11700dce45cee · Roger Ferrer / llvm-epi · GitLab

May 11, 2018
- [InstCombine] Handle atomic memset in the same way as regular memset · f6651d4d
  Daniel Neilson authored May 11, 2018
  f6651d4d
- Revert "[clang-tidy] Adding RestrictSystemIncludes check to Fuchsia module" · b262a048
  Julie Hockett authored May 11, 2018
  b262a048
- [libclang] Stop assuming that the internal C++ ABI ExceptionSpecificationType... · eedb0c95
  Richard Smith authored May 11, 2018
  eedb0c95
- [OPENMP, NVPTX] Do not use SPMD mode for target simd and target teams · df093e7b
  Alexey Bataev authored May 11, 2018
  df093e7b
- Splitting thinlto.ll test file and renaming other test files. · 304d0d55
  Rumeet Dhindsa authored May 11, 2018
  304d0d55
- [PPC64] isRelExpr should return true for the PPC Call Exprs. · c12f0511
  Sean Fertile authored May 11, 2018
  c12f0511
- Yet another follow-up to r332111. This also handles the case where an · 3a380fb2
  Adrian Prantl authored May 11, 2018
  3a380fb2
- [clang-tidy] Adding RestrictSystemIncludes check to Fuchsia module · 02aba94e
  Julie Hockett authored May 11, 2018
  02aba94e
- Move standard library inclusions to after internal inclusions. · c30365ce
  David Blaikie authored May 11, 2018
  c30365ce
- [HIP] Set proper triple and offload kind for the toolchain · f5a6b96c
  Yaxun Liu authored May 11, 2018
  f5a6b96c
- [HIP] Diagnose unsupported host triple · 00f31d51
  Yaxun Liu authored May 11, 2018
  00f31d51
- [HIP] Let clang-offload-bundler support HIP · 609f7529
  Yaxun Liu authored May 11, 2018
  609f7529
- Fix a regression in r332111. The LLDB.framework path component is not · 5103e48b
  Adrian Prantl authored May 11, 2018
  5103e48b
- [DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N) · 99d5c072
  Vedant Kumar authored May 11, 2018
  99d5c072
- [DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N) · fd340a40
  Vedant Kumar authored May 11, 2018
  fd340a40
- [DAGCombiner] Factor out duplicated logic for an extload combine, NFC (5/N) · f0e5f7c4
  Vedant Kumar authored May 11, 2018
  f0e5f7c4
- [LIT] replace output escapes wit a cdata block · d1386a88
  Chris Matthews authored May 11, 2018
  d1386a88
- Add a lock to PlatformPOSIX::DoLoadImage · d10d3795
  Frederic Riss authored May 11, 2018
  d10d3795
- [MachO] Don't write test files to /tmp, remove them afterwards. · 5fb64370
  Martin Storsjö authored May 11, 2018
  5fb64370
- make add_llvm_fuzzer calls slightly more consisten with other cmake · 06b0c2fe
  Nico Weber authored May 11, 2018
  06b0c2fe
- HostInfoMacOSX: Share the clang resource directory with Swift. · 7d46f0e4
  Adrian Prantl authored May 11, 2018
  7d46f0e4
- [InstCombine] snprintf optimizations · cd93c4ef
  David Bolvansky authored May 11, 2018
  cd93c4ef
- [X86][BtVer2] Model ymm move as double pumped instructions · 661ae777
  Simon Pilgrim authored May 11, 2018
  661ae777
- [X86] Fix the file header name on fmaintrin.h · 65ef3280
  Craig Topper authored May 11, 2018
  65ef3280
- [RISCV] Support .option rvc and norvc assembler directives · bca0c3cd
  Alex Bradbury authored May 11, 2018
  bca0c3cd
- [Analysis] Validate the return type of s(n)printf like libcalls · 0d7c3775
  Martin Storsjö authored May 11, 2018
  0d7c3775
- [Hexagon] Implement checking arguments of builtin calls · 45850687
  Krzysztof Parzyszek authored May 11, 2018
  45850687
- [X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classes · 706403ba
  Simon Pilgrim authored May 11, 2018
  706403ba
- [AArch64] Fix performPostLD1Combine to check for constant lane index. · 60460268
  Geoff Berry authored May 11, 2018
  60460268
- [mips] Rename Filler to MipsDelaySlotFiller and initialize the pass · ae201081
  Simon Dardis authored May 11, 2018
  ae201081
- Use iteration instead of recursion in CFIInserter · 82105e2a
  Sanjoy Das authored May 11, 2018
  82105e2a
- [Reassociate] Prevent infinite loops when processing PHIs. · 6e1f7bf3
  Davide Italiano authored May 11, 2018
  6e1f7bf3
- Remove unused SyncExecutor and make it clearer that the whole file is only... · 0f2a48c1
  Nico Weber authored May 11, 2018
  0f2a48c1
- [mips] Enable disassembly of fused (negative) multiply add/sub instructions · d4169ad7
  Simon Dardis authored May 11, 2018
  d4169ad7
- [X86][SLM] Vector stores only use the MEC port. · 032a01f7
  Simon Pilgrim authored May 11, 2018
  032a01f7
- [winasan] Update GetInstructionSize for Win10 1803 · 868b31bf
  David Major authored May 11, 2018
  868b31bf
- [X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector width · 22dd72b9
  Simon Pilgrim authored May 11, 2018
  22dd72b9
- [InstCombine] Unify handling of atomic memtransfer with non-atomic memtransfer · 8f30ec65
  Daniel Neilson authored May 11, 2018
  8f30ec65
- [ASan] Fix range check in AddrIsInHighShadow · 49fcf17d
  David Major authored May 11, 2018
  49fcf17d
- [X86] Assume alignment of movdir64b dst argument · 9cd4f166
  Gabor Buella authored May 11, 2018
  9cd4f166