Commits · f6ee45e94391ef8cee67e2a4ad6d61c614985de9 · Roger Ferrer / llvm-epi · GitLab

Feb 19, 2022
- [X86] Add some add reduction tests for values that are zero in the upper bits · f6ee45e9
  Simon Pilgrim authored Feb 19, 2022
  f6ee45e9
- [AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt. · c69af70f
  Micah Weston authored Feb 19, 2022
  c69af70f
- [AArch64] Common patterns between UMULL and int_aarch64_neon_umull · b8801ba0
  David Green authored Feb 19, 2022
  b8801ba0
- [RISCV] Add IsRV32 to the isel pattern for ZIP_RV32/UNZIP_RV32. NFC · 54899695
  Craig Topper authored Feb 18, 2022
  54899695
- [SelectionDAG][X86] Support f16 in getReciprocalOpName. · 1df8efae
  Craig Topper authored Feb 18, 2022
  1df8efae
- [LoongArch] Fix atomic instructions operands sequence · efb38326
  Weining Lu authored Feb 19, 2022
  efb38326
- Revert "[SelectionDAG][X86] Support f16 in getReciprocalOpName." · 0d59a54c
  Craig Topper authored Feb 18, 2022
  0d59a54c
- [SelectionDAG][X86] Support f16 in getReciprocalOpName. · 86b5e256
  Craig Topper authored Feb 18, 2022
  86b5e256
Feb 18, 2022
- [SDAG] fold sub-of-shift to add-of-shift · a2963d87
  Sanjay Patel authored Feb 18, 2022
  a2963d87
- [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. · f510045d
  Jay Foad authored Jan 14, 2022
  f510045d
- [AMDGPU] Fix kill flag on overlapping sgpr copy · 1f0aadfa
  Sebastian Neubauer authored Feb 17, 2022
  1f0aadfa
- [X86] Add test cases for sub with select. · 03ec026e
  Luo, Yuanke authored Feb 18, 2022
  
  03ec026e
- [VE] Enable v256 fcmp true|false tests · f2742302
  Simon Moll authored Feb 18, 2022
  f2742302
- [VE] Fix vmp0 subregister mapping · d46e4983
  Simon Moll authored Feb 18, 2022
  d46e4983
- Add "REQUIRES: asserts" to test misched-predicate-virtreg.mir which uses "-debug-only". · acc08a2f
  Douglas Yung authored Feb 18, 2022
  
  acc08a2f
- Revert "[XCOFF][llvm-objdump] change the priority of symbols with" · 0bf3fec4
  esmeyi authored Feb 18, 2022
  0bf3fec4
- [XCOFF][llvm-objdump] change the priority of symbols with · 2ad66217
  esmeyi authored Feb 18, 2022
  2ad66217
- [MachineOutliner] Add testcase for instruction mapping stats · 77cf18fa
  Jessica Paquette authored Feb 17, 2022
  77cf18fa
- [LoongArch] Fix several instruction definition errors in initial patches · 79b0fa08
  Weining Lu authored Feb 18, 2022
  79b0fa08
- [LoongArch] Add missing dollar prefix to register name in InstPrinter · 1d91537c
  Weining Lu authored Feb 17, 2022
  1d91537c
- [RISCV][NFC] Add some tail agnostic tests for nomask operations. · c6a3225b
  Zakk Chen authored Feb 16, 2022
  c6a3225b
- [RISCV][NFC] Add tail agnostic tests for nomask Vector Reduction IR intrinsics. · 6f6ac4af
  Zakk Chen authored Feb 16, 2022
  6f6ac4af
- [WebAssembly] Make EH/SjLj vars unconditionally thread local · 4f9b8397
  Heejin Ahn authored Feb 16, 2022
  4f9b8397
- AMDGPU: Try to fix expensive_checks bot tests failures · ba653b7f
  Matt Arsenault authored Feb 17, 2022
  
  ba653b7f
- RegAllocGreedy: Fix last chance recolor assert in impossible case · c46aab01
  Matt Arsenault authored Feb 17, 2022
  c46aab01
Feb 17, 2022
- [AArch64] Add extra widening mul tests. NFC · bd8db271
  David Green authored Feb 17, 2022
  bd8db271
- [AMDGPU] Promote recursive loads from kernel argument to constant · b0aa1946
  Stanislav Mekhanoshin authored Feb 11, 2022
  b0aa1946
- [X86ISelLowering] permit BlockAddressSDNode "i" constraints for PIC · 027c16be
  Nick Desaulniers authored Feb 17, 2022
  027c16be
- [SystemZ] Improve emission of alignment hints. · cf426100
  Jonas Paulsson authored Feb 17, 2022
  cf426100
- [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics. · ca783124
  Zakk Chen authored Feb 15, 2022
  ca783124
- [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo · fc1b2122
  Kerry McLaughlin authored Feb 17, 2022
  fc1b2122
- [RISCV] Match shufflevector corresponding to slideup. · bbee9e77
  Craig Topper authored Feb 17, 2022
  bbee9e77
- [RISCV] Fix incorrect MemOperand copy converting splat+load to vlse. · 954fe404
  Craig Topper authored Feb 17, 2022
  954fe404
- [AArch64] Add some missing strict FP vector lowering · 8e17c961
  John Brawn authored Jan 25, 2022
  8e17c961
- [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations · 2f2dcb4f
  Matt Devereau authored Feb 08, 2022
  2f2dcb4f
- [RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics. · eeb7754f
  Zakk Chen authored Feb 13, 2022
  eeb7754f
- [X86] selectLEAAddr - add X86ISD::SMUL/UMULO handling · 3f22a496
  Simon Pilgrim authored Feb 17, 2022
  3f22a496
- [DAGCombiner] Extend ISD::ABDS/U combine to handle more cases. · 6457f42b
  Paul Walker authored Dec 10, 2021
  6457f42b
- [DAG] Fix in ReplaceAllUsesOfValuesWith · 1a8bdf95
  Bjorn Pettersson authored Feb 04, 2022
  1a8bdf95
- [AArch64] Allow strict opcodes in faddp patterns · d916856b
  John Brawn authored Jan 28, 2022
  d916856b