Commits · f7dd6069a546233627f33abe0358477c7e917352 · Roger Ferrer / llvm-epi · GitLab

May 03, 2018
- [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes · f7dd6069
  Simon Pilgrim authored May 03, 2018
  f7dd6069
- ARM: don't try to over-align large vectors as arguments. · 28e0a6f7
  Tim Northover authored May 03, 2018
  28e0a6f7
- perform DSE through launder.invariant.group · c77ab8ef
  Piotr Padlewski authored May 03, 2018
  c77ab8ef
- Rename invariant.group.barrier to launder.invariant.group · 5dde8094
  Piotr Padlewski authored May 03, 2018
  5dde8094
- [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and... · 93c878c7
  Simon Pilgrim authored May 03, 2018
  93c878c7
- [WebAssembly] MC: Don't litter test directory. · 281919f5
  Benjamin Kramer authored May 03, 2018
  281919f5
- Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)" · 67fdea49
  Martin Storsjö authored May 03, 2018
  67fdea49
- [LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the... · 856fd686
  Craig Topper authored May 03, 2018
  856fd686
- [LoopIdiomRecognize] Add a test case showing that we transform to ctpop... · a0cba89f
  Craig Topper authored May 03, 2018
  a0cba89f
- Re-enable "[SCEV] Make computeExitLimit more simple and more powerful" · 58fce7e5
  Max Kazantsev authored May 03, 2018
  58fce7e5
- MachineInst support mapping SDNode fast math flags for support in Back End code generation · 7d1b25d0
  Michael Berg authored May 03, 2018
  7d1b25d0
- [PowerPC] Implement isMaskAndCmp0FoldingBeneficial · 01e2e79a
  Nemanja Ivanovic authored May 02, 2018
  01e2e79a
- [WebAssembly] MC: Create and use first class section symbols · 4d57fbd0
  Sam Clegg authored May 02, 2018
  4d57fbd0
- [PowerPC] No CTR loop if the candidate exiting block is in a different loop · 2139e99e
  Nemanja Ivanovic authored May 02, 2018
  2139e99e
- [GCOV] Emit the writeout function as nested loops of global data. · 71c3a3fa
  Chandler Carruth authored May 02, 2018
  71c3a3fa
May 02, 2018
- [llvm-rc] Default to writing the output next to the input, if no output is specified · e3b43793
  Martin Storsjö authored May 02, 2018
  e3b43793
- [llvm-cvtres] Allow parameters preceded by '-' in addition to '/' · ca169789
  Martin Storsjö authored May 02, 2018
  ca169789
- [llvm-objcopy] Add --discard-all (-x) option · 41695f8e
  Paul Semel authored May 02, 2018
  41695f8e
- [llvm-objcopy] Add --weaken option · 2c0510f0
  Paul Semel authored May 02, 2018
  2c0510f0
- [GlobalISel][InstructionSelect] Refactoring out a getMatchTable virtual method + other small NFC's · 2df4c229
  Roman Tereshin authored May 02, 2018
  2df4c229
- [llvm-rc] Add rudimentary support for codepages · d1d046aa
  Martin Storsjö authored May 02, 2018
  d1d046aa
- [X86][SNB] Fix scheduling of MMX integer multiply instructions. · 350c22c5
  Simon Pilgrim authored May 02, 2018
  350c22c5
- [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM... · 6732f6ea
  Simon Pilgrim authored May 02, 2018
  6732f6ea
- [COFF, ARM64] Hook up a few remaining relocations · d0b5034b
  Martin Storsjö authored May 02, 2018
  d0b5034b
- [AMDGPU] A trivial fix for a buildbot failure caused by "commit... · 07e61234
  Farhana Aleen authored May 02, 2018
  07e61234
- [reassociate] Fix excessive revisits when processing long chains of reassociatable instructions. · 8d0d1aa2
  Daniel Sanders authored May 02, 2018
  8d0d1aa2
- [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes... · 819f218f
  Simon Pilgrim authored May 02, 2018
  819f218f
- Revert "[AMDGPU] performAddCombine should run after DAG is legalized." · 150cb6d9
  Farhana Aleen authored May 02, 2018
  150cb6d9
- [AMDGPU] performAddCombine should run after DAG is legalized. · 2f4100f5
  Farhana Aleen authored May 02, 2018
  2f4100f5
- [X86] Fix scheduling info for (V?)SQRTPDm on silvermont. · a1a3095d
  Clement Courbet authored May 02, 2018
  a1a3095d
- [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions. · 659a48cd
  Sander de Smalen authored May 02, 2018
  659a48cd
- [TableGen] Don't quote variable name when printing !foreach. · 6a02604e
  Simon Tatham authored May 02, 2018
  6a02604e
- [AArch64][SVE] Asm: Support for scatter ST1 store instructions. · 57da042e
  Sander de Smalen authored May 02, 2018
  57da042e
- Revert "[mips] Correct the predicates of sign extension instructions" · 694fde21
  Simon Dardis authored May 02, 2018
  694fde21
- [mips] Correct the predicates of sign extension instructions · 7a36495b
  Simon Dardis authored May 02, 2018
  7a36495b
- [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions. · 414d2358
  Sander de Smalen authored May 02, 2018
  414d2358
- [mips] Correct the predicates for shifts. · 6cfc9ba5
  Simon Dardis authored May 02, 2018
  6cfc9ba5
- [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values · e93fd5f1
  Simon Pilgrim authored May 02, 2018
  e93fd5f1
- [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions. · c1e44bdf
  Sander de Smalen authored May 02, 2018
  c1e44bdf
- Mark invariant.group.barrier as inaccessiblememonly · f801205e
  Piotr Padlewski authored May 02, 2018
  f801205e