Commits · f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4 · Roger Ferrer / llvm-epi · GitLab

Jan 22, 2021
- [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions · f8f1b20e
  Craig Topper authored Jan 21, 2021
  f8f1b20e
- [AArch64][GlobalISel] Make G_USUBO legal and select it. · 3dedad47
  Cassie Jones authored Jan 21, 2021
  3dedad47
- [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7 · 96677503
  ShihPo Hung authored Jan 20, 2021
  96677503
- [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0 · 976cf53c
  ShihPo Hung authored Jan 19, 2021
  976cf53c
- [RISCV] Add intrinsics for RVV 1.0 vrgatherei16 · bea661d9
  ShihPo Hung authored Jan 18, 2021
  bea661d9
- [Inlining] Delete redundant optnone/alwaysinline check · bd3ca666
  Xun Li authored Jan 21, 2021
  bd3ca666
- [PowerPC] Duplicate inherited heuristic from base scheduler · 449f2f71
  Qiu Chaofan authored Jan 22, 2021
  449f2f71
- [AMDGPU] Test case demonstrating issues with generation of .debug_frame · b6c3a59c
  RamNalamothu authored Jan 22, 2021
  b6c3a59c
- [llvm-mca] Addressing build failures due to missing override specifiers · c6e8f814
  Wolfgang Pieb authored Jan 21, 2021
  
  c6e8f814
- [RISCV] Add a VL output to vleff intrinsics. · 3b5430eb
  Craig Topper authored Jan 21, 2021
  3b5430eb
- [NFC] [TargetRegisterInfo] add another API to get srcreg through copy. · 8120cfed
  Chen Zheng authored Jan 18, 2021
  8120cfed
- [llvm-mca] Test case was missing a triple. · 020c00b5
  Wolfgang Pieb authored Jan 21, 2021
  
  020c00b5
- [RISCV] Use v8-v23 as argument registers to conform to the proposal. · 6e360460
  Hsiangkai Wang authored Jan 21, 2021
  6e360460
- [llvm-mca] Forgot a couple of override specifiers. · 04af1ca2
  Wolfgang Pieb authored Jan 21, 2021
  04af1ca2
- [RISCV] New vector load/store in V extension v1.0 · b7ab6726
  Hsiangkai Wang authored Dec 21, 2020
  b7ab6726
- [gn build] Port d38be2ba · 0cd1e473
  LLVM GN Syncbot authored Jan 21, 2021
  
  0cd1e473
- [llvm-mca] Initial implementation of serialization using JSON. The views · d38be2ba
  Wolfgang Pieb authored Jan 21, 2021
  d38be2ba
Jan 21, 2021
- [WebAssembly] Test that invalid symbol/relocation types generate errors · d75b3719
  Sam Clegg authored Jan 21, 2021
  d75b3719
- [LV][ARM] Inloop reduction cost modelling · 39db5753
  David Green authored Jan 21, 2021
  39db5753
- [SLP] rename reduction variable to avoid shadowing; NFC · 2f03528f
  Sanjay Patel authored Jan 21, 2021
  2f03528f
- Scalar: Don't visit constants in findInnerReductionPhi in LoopInterchange · bfec9148
  Anton Rapetov authored Jan 21, 2021
  bfec9148
- ADT: Fix reference invalidation in SmallVector::emplace_back and assign(N,V) · d7ff0036
  Duncan P. N. Exon Smith authored Jan 14, 2021
  d7ff0036
- Recommit "[RISCV] Legalize select when Zbt extension available" · 4ab0f51a
  Michael Munday authored Jan 21, 2021
  4ab0f51a
- [SLP] simplify reduction matching · d7775338
  Sanjay Patel authored Jan 21, 2021
  d7775338
- [FunctionAttrs] Infer willreturn for functions without loops · 65fd034b
  Nikita Popov authored Jan 13, 2021
  65fd034b
- X86: Fix use-after-realloc in X86AsmParser::ParseIntelExpression · f2fd41d7
  Duncan P. N. Exon Smith authored Jan 20, 2021
  f2fd41d7
- [NFC][Doc] Mention SystemZ supports StackMap generation · b3a5abcb
  Ulrich Weigand authored Jan 21, 2021
  b3a5abcb
- [RISCV] Update V instructions constraints to conform to v1.0 · b8921af6
  Hsiangkai Wang authored Dec 28, 2020
  b8921af6
- Revert "[AMDGPU] Implement mir parseCustomPseudoSourceValue" · 4dbdff66
  Sebastian Neubauer authored Jan 21, 2021
  4dbdff66
- [RISCV] Add new V instructions in v1.0-08a0b46. · 266820be
  Hsiangkai Wang authored Dec 21, 2020
  266820be
- [RISCV] Make LMUL field in VTYPE continuous. · 9dd5aea1
  Hsiangkai Wang authored Dec 21, 2020
  9dd5aea1
- [AMDGPU][GlobalISel] Run SIAddImgInit · c0b3c5a0
  Jay Foad authored Jan 21, 2021
  c0b3c5a0
- AMDGPU: Remove v_rsq_f64 patterns · 94375d10
  Matt Arsenault authored Jan 20, 2021
  94375d10
- AMDGPU: Use more accurate fast f64 fdiv · 2a0db8d7
  Matt Arsenault authored Jan 20, 2021
  2a0db8d7
- AArch64/GlobalISel: Factor out parametersInCSRMatch · 35c535a7
  Matt Arsenault authored Jan 12, 2021
  35c535a7
- [AMDGPU] Implement mir parseCustomPseudoSourceValue · ba7dcd85
  Sebastian Neubauer authored Jan 15, 2021
  ba7dcd85
- [ARM] Fix vector saddsat costs. · dfac521d
  David Green authored Jan 21, 2021
  dfac521d
- [OpenMP] Add support for mapping names in mapper API · e4eaf9d8
  Joseph Huber authored Jan 15, 2021
  e4eaf9d8
- AMDGPU: Add occupancy to serialized MachineFunctionInfo · 20566a2e
  Matt Arsenault authored Jan 15, 2021
  20566a2e
- [InstCombine] avoid crashing on attribute propagation · 070af1b7
  Sanjay Patel authored Jan 21, 2021
  070af1b7