Commits · f9235e45fd1f5ca21f95105427184a6afd0f9d95 · Roger Ferrer / llvm-epi · GitLab

Dec 08, 2021
- A new hidden option test-changed=exe that calls exe after each time IR changes · f9235e45
  Jamie Schmeiser authored Dec 08, 2021
  f9235e45
- Revert "[Symbolizer][Debuginfo] Add debuginfod client to llvm-symbolizer." · aaec63d2
  Noah Shutty authored Dec 08, 2021
  aaec63d2
- [CostModel][X86] Split MUL/SDIV+SREM/UDIV+UREM PowerOf2 handling. NFC. · 30e38d67
  Simon Pilgrim authored Dec 08, 2021
  30e38d67
- [Symbolizer][Debuginfo] Add debuginfod client to llvm-symbolizer. · 02cc8d69
  Noah Shutty authored Dec 08, 2021
  02cc8d69
- [NFC][CodeGen] Remove rarely used DL variable from SelectionDAGBuilder · 3257f63b
  David Sherwood authored Nov 23, 2021
  3257f63b
- [Support] improve known bits analysis for multiply by power-of-2 (1 set bit) · e9179a6a
  Sanjay Patel authored Dec 08, 2021
  e9179a6a
- [amdgpu][nfc] Move non-shared code out of LDSUtils · f0e3b39a
  Jon Chesterfield authored Dec 08, 2021
  
  f0e3b39a
- [ARM] Peek through And 1 in IsCMPZCSINC · d43c801d
  David Green authored Dec 08, 2021
  d43c801d
- [InstCombine] try to fold div with constant dividend and select-of-constants divisor · a7ed21aa
  Sanjay Patel authored Dec 08, 2021
  a7ed21aa
- [LAA] Use type sizes when determining dependence. · 77b2bb55
  Jolanta Jensen authored Dec 06, 2021
  77b2bb55
- Remove Colours array in -print-changed=dot-cfg · 84687405
  Jamie Schmeiser authored Dec 08, 2021
  84687405
- [VE] Change error handling of data references · e71fa033
  Kazushi (Jam) Marukawa authored Dec 06, 2021
  e71fa033
- [X86] LowerRotate - split 512-bit integers on non 512-bit BWI targets. · 7bffc547
  Simon Pilgrim authored Dec 08, 2021
  
  7bffc547
- [SVE][InstCombine] Support more cases where ld1/st1 can be lowered to load/store instructions. · 01bc67e4
  Paul Walker authored Dec 03, 2021
  01bc67e4
- [SDAG] Refine MMO size when converting masked load/store to normal load/store · 5d7efd47
  David Green authored Dec 08, 2021
  5d7efd47
- Allow DataLayout to support arbitrary pointer sizes · 0fcb16ee
  Stephen Neuendorffer authored Nov 18, 2021
  0fcb16ee
- [CostModel][X86] Add i64 mul cost for avx512 as 1cy · d2c093e7
  Haohai Wen authored Dec 07, 2021
  d2c093e7
- [ORC] Add a MaterializationUnit::Interface struct. · ae73f3fd
  Lang Hames authored Dec 08, 2021
  ae73f3fd
- [macho] add support for emitting macho files with two build version load commands · 0756aa39
  Alex Lorenz authored Dec 07, 2021
  0756aa39
- [PowerPC] use lvx + splat directly for aligned splat load · 63cd1842
  Chen Zheng authored Nov 16, 2021
  63cd1842
- Revert "Revert "Use VersionTuple for parsing versions in Triple, fixing issues... · 219672b8
  James Farrell authored Dec 06, 2021
  219672b8
- Revert "[RISCV] Add target specific loop unrolling and peeling preferences" · 3e363f14
  Michael Berg authored Dec 07, 2021
  3e363f14
- [RISCV] Add target specific loop unrolling and peeling preferences · 8487981a
  Michael Berg authored Dec 07, 2021
  8487981a
Dec 07, 2021
- Revert "CycleInfo: Introduce cycles as a generalization of loops" · 02940d6d
  Jonas Devlieghere authored Dec 07, 2021
  02940d6d
- [InstCombine] try to fold rem with constant dividend and select-of-constants divisor · f65be726
  Sanjay Patel authored Dec 07, 2021
  f65be726
- [VP] Cost model for VPMemory operations on PowerPC. · 8aee7833
  Bardia Mahjour authored Dec 06, 2021
  8aee7833
- [NFC][CodeView] Use one unified access to the module in beginModule. · b5c42ef3
  Chih-Ping Chen authored Dec 07, 2021
  b5c42ef3
- Remove unused variable. NFC. · d298c324
  Simon Pilgrim authored Dec 07, 2021
  
  d298c324
- [SystemZ] Add range checks for PC-relative fixups. · 5bf4f2ac
  Jonas Paulsson authored Nov 18, 2021
  5bf4f2ac
- [DAG] Update expandFunnelShift/expandROT to return the expansion directly. NFCI. · 52d2f353
  Simon Pilgrim authored Dec 07, 2021
  52d2f353
- [NFC] Clarify comment about LoopDeletionPass in the optimization pipeline · 5c7e783e
  Arthur Eubanks authored Dec 06, 2021
  5c7e783e
- [RISCV] Revise RISCVInstPrinter::printVTypeI to not assume there are 3 invalid vtype bits. · 622d6894
  Craig Topper authored Dec 07, 2021
  622d6894
- [llvm] Use range-based for loops (NFC) · 630c847b
  Kazu Hirata authored Dec 07, 2021
  
  630c847b
- [mlgo][regalloc] Add score calculation for training · fa99cb64
  Mircea Trofin authored Dec 06, 2021
  fa99cb64
- [VPlan] Verify plan entry and exit blocks, set correct exit block. · e9a29444
  Florian Hahn authored Dec 07, 2021
  e9a29444
- [AMDGPU] Mark time intrinsics as nomem, hassideeffects · 077a14e0
  Jay Foad authored Dec 07, 2021
  077a14e0
- [InstSimplify] add logic fold for 'or' with 'xor'+'and' · 8a69b044
  Sanjay Patel authored Dec 07, 2021
  8a69b044
- [RISCV] Replace uses of RISCVOpcode<0b0010011> and RISCVOpcode<0b0011011> with... · 2a9b2444
  Craig Topper authored Dec 07, 2021
  2a9b2444
- ext-tsp basic block layout · f573f686
  spupyrev authored Nov 08, 2021
  f573f686
- [MIPS] Add FPU Delay Slot for MIPS1/2/3 · f0f6bba5
  Djordje Todorovic authored Dec 07, 2021
  f0f6bba5