Commits · fa78983bcb355bbe9a3cf40870a2378d03ffb591 · Roger Ferrer / llvm-epi · GitLab

Jul 07, 2023
- [PEI][Mips] Switch to backwards frame index elimination · fa78983b
  Jay Foad authored Jun 08, 2023
  fa78983b
- [PEI] Simplify iterator handling in replaceFrameIndicesBackward. NFCI. · 4fd186d8
  Jay Foad authored Jun 06, 2023
  4fd186d8
- [AMDGPU] Enable whole wave register copy · b4a62b1f
  Christudasan Devadasan authored Jul 07, 2023
  b4a62b1f
- [AMDGPU] Implement whole wave register spill · b78b36e1
  Christudasan Devadasan authored Jul 07, 2023
  b78b36e1
- [CodeGen]Allow targets to use target specific COPY instructions for live range splitting · b7836d85
  Yashwant Singh authored Jul 07, 2023
  b7836d85
- [LLVM-C] Use unwrapDI in LLVMDITypeGetName · eb98abab
  Tamir Duberstein authored Jul 07, 2023
  eb98abab
- Appease clang-tidy · 54eafd1b
  Tamir Duberstein authored Jul 07, 2023
  54eafd1b
- revert filter_iterator_impl::operator++ changes · 787b5ad7
  Alex Brachet authored Jul 07, 2023
  
  787b5ad7
- [RISCV] Add a guard condition to orc_b/brev8 handling in ReplaceNodeResults. · 6f908080
  Craig Topper authored Jul 07, 2023
  6f908080
- [RISCV] Remove pseudos for vwcvt.f.x(u) with rounding mode. · 427278d1
  Craig Topper authored Jul 07, 2023
  427278d1
- [ADT] fix postfix filter_iterator_impl::operator++ · 1882a4ee
  Alex Brachet authored Jul 07, 2023
  
  1882a4ee
- Reland: "[ADT] fix filter_iterator_impl::operator++" · 1c362267
  Alex Brachet authored Jul 07, 2023
  
  1c362267
- [PowerPC] Update InputOps of Power10 SchedModel · a2b5117d
  Qiu Chaofan authored Jul 07, 2023
  a2b5117d
- [RISCV] Update loop vectorizer interleaved access test output · b9af0862
  Luke Lau authored Jul 07, 2023
  b9af0862
- [RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores · 02bb33c3
  Luke Lau authored Jul 05, 2023
  02bb33c3
- [RISCV] Add tests for unaligned segmented loads and stores · 18013bea
  Luke Lau authored Jul 05, 2023
  18013bea
- A new code layout algorithm for function reordering [1/3] · a7e13a99
  spupyrev authored Jun 13, 2023
  a7e13a99
- [InstCombine] Handle unreachable edge when branching to loop · 143a869c
  Nikita Popov authored Jul 07, 2023
  143a869c
- Revert "[ADT] fix filter_iterator_impl::operator++" · 85a68c3c
  Alex Brachet authored Jul 07, 2023
  85a68c3c
- SimpleLoopUnswitch: Restore uniform unswitch test · 7128b127
  Matt Arsenault authored Jun 01, 2023
  7128b127
- [ADT] fix filter_iterator_impl::operator++ · 5a67fa2b
  Alex Brachet authored Jul 07, 2023
  
  5a67fa2b
- TTI: Pass function to hasBranchDivergence in a few passes · fa90f6b9
  Matt Arsenault authored Jun 02, 2023
  fa90f6b9
- AMDGPU: Remove attempt at simplifying the format string in printf lowering · 94e24624
  Matt Arsenault authored Jun 28, 2023
  94e24624
- [InstCombine] Add test for unreachable loop (NFC) · 33909c8f
  Nikita Popov authored Jul 07, 2023
  33909c8f
- [LoopVectorize] Regenerate test checks (NFC) · a5e253d6
  Nikita Popov authored Jul 07, 2023
  
  a5e253d6
- InstCombine: Fold ldexp(ldexp(x, a), b) -> ldexp(x, a + b) · 4f9aad96
  Matt Arsenault authored Jul 04, 2023
  4f9aad96
- InstCombine: Add baseline tests for ldexp reassociation combine · d362aab2
  Matt Arsenault authored Jul 04, 2023
  
  d362aab2
- InstSimplify: Update another cannotBeOrderedLessThanZero use · db58a9c0
  Matt Arsenault authored Apr 25, 2023
  db58a9c0
- [gn build] Port fc9821a8 · 7a749fe9
  LLVM GN Syncbot authored Jul 07, 2023
  
  7a749fe9
- [gn build] Port c0221e00 · 7d06b498
  LLVM GN Syncbot authored Jul 07, 2023
  
  7d06b498
- Revert "[DWARF][BOLT] Implement new mechanism for DWARFRewriter" · de7781ea
  Nico Weber authored Jul 07, 2023
  de7781ea
- ValueTracking: Update another cannotBeOrderedLessThanZero use · 39f2fce0
  Matt Arsenault authored Apr 25, 2023
  
  39f2fce0
- ValueTracking: Update a use of cannotBeOrderedLessThanZero · 708fa7d9
  Matt Arsenault authored Apr 25, 2023
  708fa7d9
- [AArch64][RCPC3] Instruction selection for LDAP1/STL1 instructions · 54c7aec4
  Lucas Prates authored Jun 13, 2023
  54c7aec4
- [LTO] Ensure LICM hoists expensive fdiv instructions introduced by InstCombine · 905083f3
  David Sherwood authored Feb 21, 2023
  905083f3
- [LV] Do not add load to group if it moves across conflicting store. · 4d847bf4
  Florian Hahn authored Jul 07, 2023
  4d847bf4
- [RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic. · 74eac85d
  Yeting Kuo authored Jul 07, 2023
  74eac85d
- [InstCombine] Preserve inbounds when folding select of GEP · 336d7281
  Nikita Popov authored Jun 29, 2023
  336d7281
- [RISCV] Add a pass to combine `cm.pop` and `ret` insts · c0221e00
  WuXinlong authored Jul 07, 2023
  c0221e00
- [X86] Support some Intel CPUs for cpu_specific/dispatch feature · a10dccf2
  Freddy Ye authored Jul 07, 2023
  a10dccf2