Commits · fb81f06f63af9f57be66f1ef05fd47397f999f39 · Roger Ferrer / llvm-epi · GitLab

Mar 16, 2022
- [AMDGPU] Calculate RegWidth in bits in AsmParser · fb81f06f
  Joe Nash authored Mar 15, 2022
  fb81f06f
- [AMDGPU][MC][NFC] Refactored custom operands handling · 5977dfba
  Dmitry Preobrazhensky authored Mar 16, 2022
  5977dfba
- [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments · 37b37838
  Shengchen Kan authored Mar 16, 2022
  
  37b37838
- [X86] computeKnownBitsForTargetNode - add X86ISD::AND KnownBits handling · e3deb7d8
  Simon Pilgrim authored Mar 16, 2022
  e3deb7d8
- [VE] v512|256 f32|64 fneg isel and tests · 91fad116
  Simon Moll authored Mar 16, 2022
  91fad116
- Cleanup codegen includes · 989f1c72
  serge-sans-paille authored Mar 15, 2022
  989f1c72
- [LoongArch] Add some missing comments. NFC · c008a697
  Weining Lu authored Mar 16, 2022
  c008a697
- [NFC][X86] Rename some variables and functions about target features · 052d37dc
  Shengchen Kan authored Mar 16, 2022
  052d37dc
- [RISCV] Select SRLI+SLLI for AND with leading ones mask · 6a54776f
  Haocong.Lu authored Mar 16, 2022
  6a54776f
Mar 15, 2022
- X86ISelDAGToDAG: Transform TEST + MOV64ri to SHR + TEST · 84ef6212
  Matthias Braun authored Mar 09, 2022
  84ef6212
- [PowerPC][P10] Add Vector pair calling convention · 78406ac8
  Stefan Pintilie authored Mar 11, 2022
  78406ac8
- [AMDGPU] Fix typo consecutive in GCNNSAReassign · 5464fd36
  Joe Nash authored Mar 15, 2022
  
  5464fd36
- [RISCV] Remove lowerSPLAT_VECTOR · 06c5d740
  Craig Topper authored Mar 15, 2022
  06c5d740
- [VE] strided v256.23 isel and tests · 6ac3d8ef
  Simon Moll authored Mar 15, 2022
  6ac3d8ef
- [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77 · 35245356
  Ties Stuij authored Mar 15, 2022
  35245356
- Revert rG9c542a5a4e1ba36c24e48185712779df52b7f7a6 "Lower `@llvm.global_dtors`... · 7262eacd
  Simon Pilgrim authored Mar 15, 2022
  7262eacd
- Remove a top-level "using namespace" in TargetTransformInfoImpl.h · 991dc4b4
  Pavel Labath authored Mar 15, 2022
  991dc4b4
- [X86] combineSelect - canonicalize (vXi1 bitcast(iX Cond)) with... · f591231c
  Simon Pilgrim authored Mar 15, 2022
  f591231c
- [PowerPC] Disable perfect shuffle by default · 300e1293
  Qiu Chaofan authored Mar 15, 2022
  300e1293
- AMDGPU: Use removeAllRegUnitsForPhysReg() · 98dd3905
  Ruiling Song authored Jan 11, 2022
  98dd3905
- Lower `@llvm.global_dtors` using `__cxa_atexit` on MachO · 9c542a5a
  Julian Lettner authored Mar 09, 2022
  9c542a5a
- [AMDGPU] gfx940: disable OP_SEL on V_DOT instructions · c4500de2
  Stanislav Mekhanoshin authored Mar 14, 2022
  c4500de2
- [AMDGPU] Add symbolic names for gfx940 HWREGs · 8dd3d1cf
  Stanislav Mekhanoshin authored Mar 10, 2022
  8dd3d1cf
Mar 14, 2022
- [AMDGPU] Support for gfx940 flat lds opcodes · 23499103
  Stanislav Mekhanoshin authored Mar 10, 2022
  23499103
- [AMDGPU] Support gfx940 v_lshl_add_u64 instruction · 1f53f20f
  Stanislav Mekhanoshin authored Mar 10, 2022
  1f53f20f
- [AMDGPU] flat scratch SVS addressing mode for gfx940 · 36fe3f13
  Stanislav Mekhanoshin authored Mar 08, 2022
  36fe3f13
- [AMDGPU] gfx940 memory model · 47bac63d
  Stanislav Mekhanoshin authored Mar 08, 2022
  47bac63d
- [AMDGPU] Restrict machine copy propagation from creating unaligned classes · 72a9e5f8
  Stanislav Mekhanoshin authored Mar 11, 2022
  72a9e5f8
- [X86] Fix cosmetic issues in instruction mnemonics · 842fa38d
  Amir Ayupov authored Mar 14, 2022
  842fa38d
- [regalloc] Remove -consider-local-interval-cost · 294eca35
  Mircea Trofin authored Mar 07, 2022
  294eca35
- [AArch64] Perform last active true vector combine · 35683338
  zhongyunde authored Mar 15, 2022
  35683338
- [WebAssembly] Remove unused method from WebAssemblyTargetStreamer. NFC · 2f5c4083
  Sam Clegg authored Mar 12, 2022
  2f5c4083
- [OpaquePtr][AArch64] Use elementtype on ldxr/stxr · 250620f7
  Arthur Eubanks authored Feb 24, 2022
  250620f7
- [PowerPC] Add missed VSX shuffles instead of Altivec ones · 766ca2c5
  Nemanja Ivanovic authored Mar 11, 2022
  766ca2c5
- [VE] v256f32|64 fma isel · 3297571e
  Simon Moll authored Mar 14, 2022
  3297571e
- [VE] Support more intrinsics · 92605921
  Kazushi (Jam) Marukawa authored Mar 12, 2022
  92605921
- [VE] v256i32|64 reduction isel and tests · f318d1e2
  Simon Moll authored Mar 14, 2022
  f318d1e2
- [VE] v256.32|64 gather|scatter isel and tests · a5f12623
  Simon Moll authored Mar 14, 2022
  a5f12623
- [RISCV] Add basic code modeling for fixed length vector reduction. · ae7c6647
  Yeting Kuo authored Mar 11, 2022
  ae7c6647
- [RISCV] Merge ReplaceNodeResults code for SHFL and GREV/GORC. NFC · eeb3bfd7
  Craig Topper authored Mar 13, 2022
  
  eeb3bfd7