llvm-svn: 227516

llvm-svn: 227514

that's actually sitting on the target machine.

llvm-svn: 227513

calls that don't take a Function argument from Mips. Notable
exceptions: the AsmPrinter and MipsTargetObjectFile. The
latter needs to be fixed, and the former will be fixed when the
general AsmPrinter changes happen.

llvm-svn: 227512

This is just an alias for CALL64pcrel32, and we can just use that opcode
with explicit defs in the MI.

No functionality change.

llvm-svn: 227508

These are needed so this pass will produce output when
e.g. -print-after-all is used.

Phabricator Review: http://reviews.llvm.org/D7264
Patch by Geoff Berry <gberry@codeaurora.org>!

llvm-svn: 227506

win64: Call __chkstk through a register with the large code model

Fixes half of PR18582. True dynamic allocas will still have a
CALL64pcrel32 which will fail.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D7267

llvm-svn: 227503

llvm-svn: 227498

llvm-svn: 227495

llvm-svn: 227493

Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps.

llvm-svn: 227488

Add tests for the various combines. This should
always be at least cycle neutral on all subtargets for f64,
and faster on some. For f32 we should prefer selecting
v_mad_f32 over v_fma_f32.

llvm-svn: 227484

llvm-svn: 227483

llvm-svn: 227482

The use of the DbgLoc in FastISel is probably something we should fix.
It's prone to leaking the wrong location into instructions - we should
have a clear chain of custody from the debug location of an IR
Instruction to that of a MachineInstr to avoid such leakage.

llvm-svn: 227481

Any code creating an MCSectionELF knows ELF and already provides the flags.

SectionKind is an abstraction used by common code that uses a plain
MCSection.

Use the flags to compute the SectionKind. This removes a lot of
guessing and boilerplate from the MCSectionELF construction.

llvm-svn: 227476

llvm-svn: 227474

llvm-svn: 227463

llvm-svn: 227462

The schedule model is not complete yet, and could be improved.

llvm-svn: 227461

llvm-svn: 227460

For large stack offsets the compiler generates multiple immediate mode
sub/add instructions in the prologue/epilogue.  This patch makes the
compiler place the final amount to be added/subtracted into a register,
which is then added/substracted with a single operation.

Differential Revision: http://reviews.llvm.org/D7226

llvm-svn: 227458

llvm-svn: 227457

Patch by Nemanja Ivanovic.

As was uncovered by the failing test case (when run on non-PPC
platforms), the feature set when compiling with -march=ppc64le was not
being picked up. This change ensures that if the -mcpu option is not
specified, the correct feature set is picked up regardless of whether
we are on PPC or not.

llvm-svn: 227455

Only the specific ones (MergeableConst4, MergeableConst8, MergeableConst16) are
handled specially.

llvm-svn: 227440

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.

llvm-svn: 227430

correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

llvm-svn: 227402

correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

llvm-svn: 227401

llvm-svn: 227400

away from getSubtargetImpl.

llvm-svn: 227399

llvm-svn: 227386

llvm-svn: 227379

llvm-svn: 227376

llvm-svn: 227374

Differential Revision: http://reviews.llvm.org/D5820

llvm-svn: 227373

llvm-svn: 227355

[Hexagon] Updating many V4 intrinsic patterns.  Adding missing instruction and deleting unused classes.

llvm-svn: 227353

llvm-svn: 227347

llvm-svn: 227338

llvm-svn: 227335