Commits · fbee8574ab2e0656229bbb7ccd220ae22e95f8d9 · Roger Ferrer / llvm-epi · GitLab

Apr 19, 2018
- [if-converter] Handle BBs that terminate in ret during diamond conversion · fbee8574
  Krzysztof Parzyszek authored Apr 19, 2018
  fbee8574
- [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTOR · 2a9a83cd
  Krzysztof Parzyszek authored Apr 19, 2018
  2a9a83cd
- [AMDGPU] Do not only rely on BB number when finding bottom loop · 1bc6e71f
  Mark Searles authored Apr 19, 2018
  1bc6e71f
- [Hexagon] Generate code for vector bswap intrinsics · d92c37e0
  Krzysztof Parzyszek authored Apr 19, 2018
  d92c37e0
- [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops · 23bcf06a
  Krzysztof Parzyszek authored Apr 19, 2018
  23bcf06a
- [mips] Correct the definitions of the unaligned word memory operation instructions · 5d61c8b2
  Simon Dardis authored Apr 19, 2018
  5d61c8b2
- Lowering x86 adds/addus/subs/subus intrinsics (llvm part) · e8fed154
  Alexander Ivchenko authored Apr 19, 2018
  e8fed154
- [ARM] Add some missing FP16 VSEL test cases · a79ea80d
  Sjoerd Meijer authored Apr 19, 2018
  a79ea80d
- [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs. · f846e2d1
  Craig Topper authored Apr 19, 2018
  f846e2d1
Apr 18, 2018
- [NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 variants of wmma instructions. · 0ae85903
  Artem Belevich authored Apr 18, 2018
  0ae85903
- [RISCV] Add test changes missed from rL330293 · 9891ba34
  Alex Bradbury authored Apr 18, 2018
  9891ba34
- [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits · 3ff2022b
  Alex Bradbury authored Apr 18, 2018
  3ff2022b
- [RISCV] Add imm-cse.ll test case · 792547b3
  Alex Bradbury authored Apr 18, 2018
  792547b3
- [NFC] test case clean up · 829cd8e2
  Lei Huang authored Apr 18, 2018
  829cd8e2
- [RISCV] Expand codegen -> compression sanity checks and move to a single file · c0464d92
  Alex Bradbury authored Apr 18, 2018
  c0464d92
- Revert "[RISCV] implement li pseudo instruction" · 099c7204
  Alex Bradbury authored Apr 18, 2018
  099c7204
- [Power9]Legalize and emit code for converting Unsigned HWord/Char to Quad-Precision · 192c6ccf
  Lei Huang authored Apr 18, 2018
  192c6ccf
- [AArch64] Add isel pattern for v8i8->v2f32 NVCASTs. · 9de072f8
  Amara Emerson authored Apr 18, 2018
  9de072f8
- [RISCV] Add specific tests for materialising imm32hi20 constants · 75a4e525
  Alex Bradbury authored Apr 18, 2018
  75a4e525
- [Power9]Legalize and emit code for converting (Un)Signed Word to Quad-Precision · 198e6785
  Lei Huang authored Apr 18, 2018
  198e6785
- [x86] Switch EFLAGS copy lowering to use reg-reg form of testing for · ccd3ecb9
  Chandler Carruth authored Apr 18, 2018
  ccd3ecb9
- [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite uses · 1f87618f
  Chandler Carruth authored Apr 18, 2018
  1f87618f
- [AMDGPU] Fix issues for backend divergence tracking · 31f482c2
  David Stuttard authored Apr 18, 2018
  31f482c2
- Add tests for shrink wrapping and VLAs · d501a609
  Momchil Velikov authored Apr 18, 2018
  d501a609
- [X86] Give CMOV 2 cycle latency on SLM. · 513e11bb
  Craig Topper authored Apr 18, 2018
  513e11bb
- [X86] Don't crash on bad operand modifiers in inline assembly · 87046124
  Craig Topper authored Apr 18, 2018
  87046124
- [AMDGPU] Enabled v2.16 literals for VOP3P · 8b20b7dc
  Stanislav Mekhanoshin authored Apr 17, 2018
  8b20b7dc
Apr 17, 2018
- [RISCV] implement li pseudo instruction · 480b7bc9
  Alex Bradbury authored Apr 17, 2018
  480b7bc9
- LoadStoreVectorizer crashes due to unsized type · 0bee6308
  Stanislav Mekhanoshin authored Apr 17, 2018
  0bee6308
- [XRay] Typed event logging intrinsic · 3d86823f
  Keith Wyss authored Apr 17, 2018
  3d86823f
- [WebAssembly] Teach fast-isel to gracefully recover from illegal return types. · 4576dc06
  Dan Gohman authored Apr 17, 2018
  4576dc06
- [X86] Add separate scheduling class for PSADBW instruction. · e56a2fc5
  Craig Topper authored Apr 17, 2018
  e56a2fc5
- [X86] Remove -mcpu=skx/knl from some tests and use -mattr instead. · 0c47e8f3
  Craig Topper authored Apr 17, 2018
  0c47e8f3
- Revert "Fix incorrect choice of callee-saved registers save/restore points (take 2)" · c7ff2e9a
  Momchil Velikov authored Apr 17, 2018
  c7ff2e9a
- Fix incorrect choice of callee-saved registers save/restore points (take 2) · 24db1257
  Momchil Velikov authored Apr 17, 2018
  24db1257
- [Hexagon] Do not merge initializers for stack and non-stack expressions · cc712917
  Krzysztof Parzyszek authored Apr 17, 2018
  cc712917
- [PowerPC] Mark the BDNZ intrinsic as NoDuplicate · a9a6dd82
  Nemanja Ivanovic authored Apr 17, 2018
  a9a6dd82
- [X86] Add FP comparison scheduler classes · 86e3c269
  Simon Pilgrim authored Apr 17, 2018
  86e3c269
- [DAGCombiner] Fix for oss-fuzz bug · 5b4a67af
  Gerolf Hoflehner authored Apr 17, 2018
  5b4a67af
Apr 16, 2018
- [MIR-Canon] Fixing a test failure caused by COPY Folding. · 52e38353
  Puyan Lotfi authored Apr 16, 2018
  52e38353