Commits · fbee8574ab2e0656229bbb7ccd220ae22e95f8d9 · Roger Ferrer / llvm-epi · GitLab

Apr 16, 2018
- [MIR-Canon] Adding ISA-Agnostic COPY Folding. · 14b6637e
  Puyan Lotfi authored Apr 16, 2018
  14b6637e
Apr 05, 2018
- [MIR-Canon] Improving performance by switching to named vregs. · d6f7313c
  Puyan Lotfi authored Apr 05, 2018
  d6f7313c
Mar 31, 2018
- [MIR-Canon] Adding support for local idempotent instruction hoisting. · 57c4f38c
  Puyan Lotfi authored Mar 31, 2018
  57c4f38c
Mar 30, 2018
- [MIR] Adding support for Named Virtual Registers in MIR. · 399b46c9
  Puyan Lotfi authored Mar 30, 2018
  399b46c9
Mar 01, 2018
- [MIRParser] Accept overloaded intrinsic names w/o type suffixes · 12a4dc4c
  Roman Tereshin authored Feb 28, 2018
  12a4dc4c
Feb 28, 2018
- [GlobalISel] Print/Parse FailedISel MachineFunction property · 3054ecea
  Roman Tereshin authored Feb 28, 2018
  3054ecea
Feb 09, 2018
- [GISel]: Verify COPIES involving generic registers. · b14fd260
  Aditya Nandakumar authored Feb 09, 2018
  b14fd260
Jan 31, 2018
- Followup on Proposal to move MIR physical register namespace to '$' sigil. · 43e94b15
  Puyan Lotfi authored Jan 31, 2018
  43e94b15
Jan 26, 2018
- [MIR] Add support for addrspace in MIR · e4718e84
  Francis Visoiu Mistrih authored Jan 26, 2018
  e4718e84
Jan 19, 2018
- Move tests to the correct place · 8bb5228d
  Matthias Braun authored Jan 19, 2018
  8bb5228d
Jan 10, 2018
- [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. · fe6c9cbb
  Puyan Lotfi authored Jan 10, 2018
  fe6c9cbb
Dec 15, 2017
- [MIR] Add support for missing CFI directives · 5de20e03
  Francis Visoiu Mistrih authored Dec 15, 2017
  5de20e03
Nov 30, 2017
- [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output · 93ef1458
  Francis Visoiu Mistrih authored Nov 30, 2017
  93ef1458
Nov 28, 2017
- [mir] Print/Parse both MOLoad and MOStore when they occur together. · 17d277b7
  Daniel Sanders authored Nov 28, 2017
  17d277b7
Nov 02, 2017
- [AsmPrinterDwarf] Add support for .cfi_restore directive · 66d2c269
  Francis Visoiu Mistrih authored Nov 02, 2017
  66d2c269
Oct 24, 2017
- MIR: Print the register class or bank in vreg defs · 6c452834
  Justin Bogner authored Oct 24, 2017
  6c452834
Oct 19, 2017
- Canonicalize a large number of mir tests using update_mir_test_checks · d45849f7
  Justin Bogner authored Oct 18, 2017
  d45849f7
Sep 28, 2017
- MIR: Serialize CaleeSavedInfo Restored flag · 5c3e8a45
  Matthias Braun authored Sep 28, 2017
  5c3e8a45
Jul 20, 2017
- Add an ID field to StackObjects · db78273b
  Matt Arsenault authored Jul 20, 2017
  db78273b
Jul 14, 2017
- [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 1) · b1e8714a
  Geoff Berry authored Jul 14, 2017
  b1e8714a
Jul 13, 2017
- [MIR] Add support for printing and parsing target MMO flags · 6748abe2
  Geoff Berry authored Jul 13, 2017
  6748abe2
Jul 12, 2017
- Enhance synchscope representation · bb80d3e1
  Konstantin Zhuravlyov authored Jul 11, 2017
  bb80d3e1
Jun 06, 2017
- · 56d87ef5
  Vivek Pandya authored Jun 06, 2017
  56d87ef5
- CodeGen: Refactor MIR parsing · 7bda1958
  Matthias Braun authored Jun 06, 2017
  7bda1958
Feb 13, 2017
- MIR: parse & print the atomic parts of a MachineMemOperand. · b73e3090
  Tim Northover authored Feb 13, 2017
  b73e3090
Jan 18, 2017
- MIRParser: Allow regclass specification on operand · de5fea2c
  Matthias Braun authored Jan 18, 2017
  de5fea2c
Jan 05, 2017
- [AArch64] Fold some filled/spilled subreg COPYs · d46b6e80
  Geoff Berry authored Jan 05, 2017
  d46b6e80
Dec 22, 2016
- [GlobalISel] More fix for the size vs. type typo. NFC. · 3749f338
  Quentin Colombet authored Dec 22, 2016
  3749f338
Dec 09, 2016
- Move .mir tests to appropriate directories · 2c7d52a5
  Matthias Braun authored Dec 09, 2016
  2c7d52a5
Nov 21, 2016
- [AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber. · e0bf52f3
  Geoff Berry authored Nov 21, 2016
  e0bf52f3
Oct 12, 2016
- Add AArch64 unit tests · 40f93411
  Diana Picus authored Oct 12, 2016
  40f93411
Oct 06, 2016
- Move AArch64BranchRelaxation to generic code · 36919a4f
  Matt Arsenault authored Oct 06, 2016
  36919a4f
Sep 28, 2016
- [TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg(). · b124331d
  Geoff Berry authored Sep 27, 2016
  b124331d
Sep 14, 2016
- [AArch64] Simplify patchpoint/stackmap size test (r281301). NFC. · 7398b178
  Ahmed Bougacha authored Sep 13, 2016
  7398b178
Sep 13, 2016
- [AArch64] Support stackmap/patchpoint in getInstSizeInBytes · 4b972881
  Diana Picus authored Sep 13, 2016
  4b972881
Aug 25, 2016
- MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it · 1eb47368
  Matthias Braun authored Aug 25, 2016
  1eb47368
- MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it · a319e2ca
  Matthias Braun authored Aug 24, 2016
  a319e2ca
- MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it · f1b20c52
  Matthias Braun authored Aug 24, 2016
  f1b20c52
Aug 24, 2016
- MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. · 79f85b3b
  Matthias Braun authored Aug 24, 2016
  79f85b3b
Aug 01, 2016
- [AArch64] Return the correct size for TLSDESC_CALLSEQ · ab5a4c7d
  Diana Picus authored Aug 01, 2016
  ab5a4c7d