Commits · fc13bdd2db3035fc3693fec6aa086db4d1db3e4c · Roger Ferrer / llvm-epi · GitLab

Nov 30, 2016
- [lanai] Manually match 0/-1 with R0/R1. · fc13bdd2
  Jacques Pienaar authored Nov 29, 2016
  fc13bdd2
- Revert https://reviews.llvm.org/rL287679 · f57f150b
  Nemanja Ivanovic authored Nov 29, 2016
  f57f150b
Nov 29, 2016
- [AArch64] allow and-not-compare transform to form 'bics' · 47f7f30d
  Sanjay Patel authored Nov 29, 2016
  47f7f30d
- [AArch64] Add a basic SchedMachineModel for Falkor. · d34c26eb
  Chad Rosier authored Nov 29, 2016
  d34c26eb
- AMDGPU: Disallow exec as SMEM instruction operand · 640c44b8
  Matt Arsenault authored Nov 29, 2016
  640c44b8
- AMDGPU: Use SGPR_64 for argument lowerings · cdad316c
  Matt Arsenault authored Nov 29, 2016
  cdad316c
- AMDGPU: Rename flat operands to match mubuf · 97279a8c
  Matt Arsenault authored Nov 29, 2016
  97279a8c
- AMDGPU: Use else if · 437fd71f
  Matt Arsenault authored Nov 29, 2016
  437fd71f
- AMDGPU: Materialize frame index before add · f96eeec0
  Matt Arsenault authored Nov 29, 2016
  f96eeec0
- AMDGPU: Refactor immediate folding logic · ff8bb49b
  Matt Arsenault authored Nov 29, 2016
  ff8bb49b
- [AArch64] Fold spills of COPY of WZR/XZR · 7c078fc0
  Geoff Berry authored Nov 29, 2016
  7c078fc0
- Avoid repeated calls to MVT getSizeInBits and getScalarSizeInBits(). NFCI. · edccc125
  Simon Pilgrim authored Nov 29, 2016
  edccc125
- [PowerPC] Improvements for BUILD_VECTOR Vol. 1 · df1cb520
  Nemanja Ivanovic authored Nov 29, 2016
  df1cb520
- [X86] Moved getTargetConstantFromNode function so a future patch is more understandable. NFCI. · 001368ab
  Simon Pilgrim authored Nov 29, 2016
  001368ab
- [X86][SSE] Add initial support for combining target shuffles to (V)PMOVZX. · 35c47c49
  Simon Pilgrim authored Nov 29, 2016
  35c47c49
- Avoid repeated calls to MVT::getScalarSizeInBits(). NFCI. · 923020a6
  Simon Pilgrim authored Nov 29, 2016
  923020a6
- AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar branches · 0bc68811
  Tom Stellard authored Nov 29, 2016
  0bc68811
Nov 28, 2016
- MachineScheduler: Export function to construct "default" scheduler. · 115efcd3
  Matthias Braun authored Nov 28, 2016
  115efcd3
- [AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies · 0ee250ee
  Stanislav Mekhanoshin authored Nov 28, 2016
  0ee250ee
- [X86][SSE] Add initial support for combining (V)PMOVZX with shuffles. · 2228f70a
  Simon Pilgrim authored Nov 28, 2016
  2228f70a
- [x86] fix formatting; NFC · 100bc01a
  Sanjay Patel authored Nov 28, 2016
  100bc01a
- [X86][SSE] Added support for combining bit-shifts with shuffles. · 3f10e669
  Simon Pilgrim authored Nov 28, 2016
  3f10e669
- Test commit · 59168e28
  Daniel Cederman authored Nov 28, 2016
  59168e28
- [SystemZ] Fix build bot fallout from r288030 · a29bf16e
  Ulrich Weigand authored Nov 28, 2016
  a29bf16e
- [SystemZ] Support execution hint instructions · 84404f30
  Ulrich Weigand authored Nov 28, 2016
  84404f30
- [SystemZ] Support load-and-trap instructions · 2d9e3d9d
  Ulrich Weigand authored Nov 28, 2016
  2d9e3d9d
- [SystemZ] Add remaining branch instructions · 75839913
  Ulrich Weigand authored Nov 28, 2016
  75839913
- [SystemZ] Improve use of conditional instructions · 524f276c
  Ulrich Weigand authored Nov 28, 2016
  524f276c
Nov 27, 2016
- [X86][FMA4] Remove isCommutable from FMA4 scalar intrinsics. They aren't... · 17786f77
  Craig Topper authored Nov 27, 2016
  17786f77
- [X86][FMA] Add missing Predicates qualifier around scalar FMA intrinsic patterns. · 13b27a27
  Craig Topper authored Nov 27, 2016
  13b27a27
- [X86][FMA4] Add load folding support for FMA4 scalar intrinsic instructions. · ff9d4587
  Craig Topper authored Nov 27, 2016
  ff9d4587
- [X86] Add SHL by 1 to the load folding tables. · 3674f44e
  Craig Topper authored Nov 27, 2016
  3674f44e
- [X86][SSE] Add support for combining target shuffles to 128/256-bit PSLL/PSRL bit shifts · 91d6f5fb
  Simon Pilgrim authored Nov 27, 2016
  91d6f5fb
- [AVX-512] Add integer and fp unpck instructions to load folding tables. · 4fab4872
  Craig Topper authored Nov 27, 2016
  4fab4872
- [X86][SSE] Split lowerVectorShuffleAsShift ready for combines. NFCI. · cdb2ce66
  Simon Pilgrim authored Nov 27, 2016
  cdb2ce66
- [X86] Add TB_NO_REVERSE to entries in the load folding table where the... · 7ad961cc
  Craig Topper authored Nov 27, 2016
  7ad961cc
- [AVX-512] Add masked EVEX vpmovzx/sx instructions to load folding tables. · c3b3926f
  Craig Topper authored Nov 27, 2016
  c3b3926f
- [X86] Remove alignment restrictions from load folding table for some... · fb64a25b
  Craig Topper authored Nov 27, 2016
  fb64a25b
Nov 26, 2016
- [X86] Remove hasOneUse check that is redundant with the one in IsProfitableToFold. · 837ff25d
  Craig Topper authored Nov 26, 2016
  837ff25d
- [X86] Fix the zero extending load detection in... · e266e126
  Craig Topper authored Nov 26, 2016
  e266e126