Commits · fc9730376c213bd3bf3f5ff8251f1ba1f4cbfb31 · Roger Ferrer / llvm-epi · GitLab

Mar 16, 2023
- [RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1) · fc973037
  LiaoChunyu authored Mar 16, 2023
  fc973037
- [Clang][LoongArch] Implement patchable function entry · db5dfec9
  WANG Xuerui authored Mar 15, 2023
  db5dfec9
Mar 15, 2023
- Revert "[RISCV] Enable interleaved access vectorization" · fc220a1a
  Luke Lau authored Mar 15, 2023
  fc220a1a
- [RISCV] Enable interleaved access vectorization · acc03ad1
  Luke Lau authored Mar 09, 2023
  acc03ad1
- [AArch64] Add hex comments to mov-imm spellings in the InstPrinter · aba4e4d6
  Jon Roelofs authored Mar 14, 2023
  aba4e4d6
- Revert "[AArch64] Add hex comments to mov-imm spellings in the InstPrinter" · cdee83b0
  Jon Roelofs authored Mar 15, 2023
  cdee83b0
- [AArch64] Add hex comments to mov-imm spellings in the InstPrinter · 1def3141
  Jon Roelofs authored Mar 14, 2023
  1def3141
- [AArch64] Change GeneratePerfectShuffle to return one destination operand for... · 4b09d7a8
  Zain Jaffal authored Mar 15, 2023
  4b09d7a8
- [SCEV] Do not strengthen nuw/nsw flags during get[Zero,Sign]ExtendedExpr. · 484c6227
  Florian Hahn authored Mar 15, 2023
  484c6227
- [StandardInstrumentations] Verify function doesn't change if analyses are preserved · 20a7ea49
  Arthur Eubanks authored Mar 14, 2023
  20a7ea49
- [StandardInstrumentations] Rename -verify-cfg-preserved -> -verify-analysis-invalidation · 361cba22
  Arthur Eubanks authored Mar 14, 2023
  361cba22
- [X86] lzcnt-cmp.ll - enable CMOV on 32-bit LZCNT tests · 5be55100
  Simon Pilgrim authored Mar 15, 2023
  5be55100
- [FuncSpec][NFC] Command line option renaming. · 9627bcde
  Alexandros Lamprineas authored Mar 03, 2023
  9627bcde
- [DAG] Don't fold zext(logicalshift(zext(x),c)) -> logicalshift(zext(x),c) if the outer zext is free · 28a0d0e8
  Simon Pilgrim authored Mar 15, 2023
  28a0d0e8
- [Inliner] Assign dummy debug location to the memcpy for byval argument · e7a2da52
  Yuanfang Chen authored Mar 15, 2023
  e7a2da52
- [X86] Add more thorough testing of the zext(logicalshift(zext(x),c)) ->... · 2281286e
  Simon Pilgrim authored Mar 15, 2023
  2281286e
- [codegen][riscv] Emit CFI directives when using shadow call stack · ade336d6
  Paul Kirth authored Mar 02, 2023
  ade336d6
- [InstCombine] Add additional test for icmp eq/ne with bool load (NFC) · 9043cb75
  Nikita Popov authored Mar 15, 2023
  
  9043cb75
- [InstCombine] Regenerate test checks (NFC) · 5cb8381a
  Nikita Popov authored Mar 15, 2023
  
  5cb8381a
- [PassManager] Run PassInstrumentation after analysis invalidation · bfc6590e
  Arthur Eubanks authored Mar 14, 2023
  bfc6590e
- [DWARFLinker][DWARFv5] add support for DW_FORM_implicit_const form. · ede827f5
  Alexey Lapshin authored Mar 13, 2023
  ede827f5
- [AMDGPU] Update mul.ll with auto-generated checks · 6bc5aa59
  Konstantina Mitropoulou authored Mar 13, 2023
  6bc5aa59
- [X86] add-and-not.ll - add 32-bit test coverage · 4ead5891
  Simon Pilgrim authored Mar 15, 2023
  
  4ead5891
- [ASAN] Initial support memory checks on scalable vector typed allocas · de71056a
  Philip Reames authored Mar 15, 2023
  de71056a
- [AMDGPU] Avoid constant bus limitation on V_BFE GISel pattern · 723a53ca
  pvanhout authored Mar 15, 2023
  723a53ca
- [AArch64][SVE] Fix the indexed addressing mode when FI = 0. · 93b89bee
  Sander de Smalen authored Mar 15, 2023
  93b89bee
- [DAG] mergeStore - peek through truncates when finding dead store(trunc(load())) patterns · c1f81e76
  Simon Pilgrim authored Mar 15, 2023
  c1f81e76
- InstCombine: Handle folding fcmp of 0 into llvm.is.fpclass · 0d18f315
  Matt Arsenault authored Feb 06, 2023
  0d18f315
- Reapply "InstCombine: Fold is.fpclass(x, fcZero) to fcmp oeq 0" · 4109e3f1
  Matt Arsenault authored Feb 15, 2023
  4109e3f1
- [AArch64] Assembly Support for FEAT_GCS/FEAT_CHK · cb7fb737
  Archibald Elliott authored Mar 15, 2023
  cb7fb737
- [DWARFLinker][DWARFv5] Support debug_loclists. · 536f35ea
  Alexey Lapshin authored Feb 27, 2023
  536f35ea
- [DAG] Fold multiple insert_vector_elt of zero values into an AND mask · 70562607
  Simon Pilgrim authored Mar 15, 2023
  70562607
- [RISCV] Pass vector argument by stack correctly. · cf40b8a4
  Kito Cheng authored Mar 15, 2023
  cf40b8a4
- [RISCV] Precommit test to show wrong way to pass scalable FP vector on stack · ba1c7731
  Kito Cheng authored Mar 15, 2023
  ba1c7731
- [FuncSpec] Minor refactoring in statistics and debug messages. · 67fde2b9
  Alexandros Lamprineas authored Feb 22, 2023
  67fde2b9
- [InstCombine] Remove one-use limit when it can simplify to a const in the... · d99d765f
  chenglin.bi authored Mar 15, 2023
  d99d765f
- [InstCombine] Precommit tests for one-use check in icmp-range; NFC · 06afee24
  chenglin.bi authored Mar 15, 2023
  
  06afee24
- [NVPTX] Expose LDU builtins · 7258317b
  Jakub Chlanda authored Mar 03, 2023
  7258317b
- [AMDGPU] Use UniformityAnalysis in AtomicOptimizer · f90849df
  pvanhout authored Mar 14, 2023
  f90849df
- [AMDGPU] Select v_sat_pk_u8_i16 · 64b45db3
  pvanhout authored Feb 24, 2023
  64b45db3