Commits · fca6992be1f272f5e997bd510ca03c9389550c13 · Roger Ferrer / llvm-epi · GitLab

Jan 11, 2024
- [AArch64] MI Scheduler: create more LDP/STP pairs (#77565) · 75d820dc
  Sjoerd Meijer authored Jan 11, 2024
  75d820dc
Dec 22, 2023
- [AArch64] Implement spill/fill of predicate pair register classes (#76068) · 4b696895
  Momchil Velikov authored Dec 22, 2023
  4b696895
- Revert "[AArch64] Fold more load.x into load.i with large offset" · 0ccc1e7a
  Vitaly Buka authored Dec 21, 2023
  0ccc1e7a
Dec 21, 2023
- Re-land "[AArch64] Codegen support for FEAT_PAuthLR" (#75947) · 7bd17212
  Tomas Matheson authored Dec 21, 2023
  7bd17212
- Revert "[AArch64] Codegen support for FEAT_PAuthLR" · 9f0f5587
  Tomas Matheson authored Dec 21, 2023
  9f0f5587
- [AArch64] Codegen support for FEAT_PAuthLR · 5992ce90
  Tomas Matheson authored Jun 16, 2023
  5992ce90
- [AArch64] Fold more load.x into load.i with large offset · f5687636
  zhongyunde 00443407 authored Dec 18, 2023
  f5687636
- [AArch64] merge index address with large offset into base address · 32878c20
  zhongyunde 00443407 authored Nov 10, 2023
  32878c20
Dec 14, 2023
- [AArch64] ORRWrs is copy instruction when there's no implicit def of the X register (#75184) · 7649d223
  DianQK authored Dec 14, 2023
  7649d223
Dec 10, 2023
- [AArch64] Fix case of 0 dynamic alloc when stack probing (#74877) · 9930f3e2
  Oskar Wirga authored Dec 10, 2023
  9930f3e2
Dec 06, 2023
- [MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldClusterMemOps (#73778) · b7173652
  Alex Bradbury authored Dec 06, 2023
  b7173652
Nov 30, 2023
- [AArch64] Stack probing for function prologues (#66524) · cc944f50
  Momchil Velikov authored Nov 30, 2023
  cc944f50
- [AArch64] Teach areMemAccessesTriviallyDisjoint about scalable widths. (#73655) · 4d801225
  David Green authored Nov 30, 2023
  4d801225
Nov 29, 2023
- [NFC][MachineScheduler] Rename NumLoads parameter of shouldClusterMemOps to ClusterSize (#73757) · 6cf35668
  Alex Bradbury authored Nov 29, 2023
  6cf35668
Nov 22, 2023
- [llvm][TypeSize] Fix addition/subtraction in TypeSize. (#72979) · 81b7f115
  Sander de Smalen authored Nov 22, 2023
  81b7f115
Nov 06, 2023
- [AArch64] Fix missing opcode when calling `isAArch64FrameOffsetLegal` · c16b94a3
  Antonio Frighetto authored Nov 06, 2023
  c16b94a3
Nov 01, 2023
- [AArch64] Fix spillfill-sve.mir with expensive checks. · 7dc20abe
  Sander de Smalen authored Nov 01, 2023
  7dc20abe
- [AArch64] Fix spilling/filling of virtual registers in PNR regclass. (#70679) · 2efea512
  Sander de Smalen authored Nov 01, 2023
  2efea512
Oct 31, 2023
- [AArch64] Handle newly-added atomic instructions in `getMemOpInfo` · 8ce4b7bc
  Antonio Frighetto authored Oct 31, 2023
  8ce4b7bc
- [AArch64] Also implement PNR -> PNR copies. (#70682) · 73498d26
  Sander de Smalen authored Oct 31, 2023
  73498d26
Oct 27, 2023
- [SVE] Fix incorrect offset calculation when rewriting an instruction's frame index. (#70315) · 7c90be28
  Paul Walker authored Oct 27, 2023
  7c90be28
Oct 17, 2023
- [CodeGen][NFC] Fix formatting · 389958a9
  Bill Wendling authored Oct 17, 2023
  389958a9
- [CodeGen] Avoid potential sideeffects from XOR (#67193) · fbf0a77e
  Bill Wendling authored Oct 17, 2023
  fbf0a77e
- Reland: [AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG · abd0d5d2
  Vladislav Dzhidzhoev authored Aug 14, 2023
  abd0d5d2
- [AArch64] Allow only LSL to be folded into addressing mode (#69235) · bea36849
  Momchil Velikov authored Oct 17, 2023
  bea36849
Oct 12, 2023
- [AArch64] Fix incorrect big-endian spill in foldMemoryOperandImpl (#65601) · a574ef61
  john-brawn-arm authored Oct 12, 2023
  a574ef61
Oct 11, 2023
- [AArch64][PAC] Check authenticated LR value during tail call · 1d2b5582
  Anatoly Trosinenko authored Oct 11, 2023
  1d2b5582
Oct 06, 2023
- [AArch64][BTI] Prevent Machine Scheduler from moving branch targets (#68313) · f1b2dd2a
  Anatoly Trosinenko authored Oct 06, 2023
  f1b2dd2a
Oct 02, 2023
- Revert "CodeGen: Disable isCopyInstrImpl if there are implicit operands" · f7937939
  Matt Arsenault authored Oct 02, 2023
  f7937939
- CodeGen: Disable isCopyInstrImpl if there are implicit operands · bc7d88fa
  Matt Arsenault authored Jul 26, 2023
  bc7d88fa
Sep 26, 2023
- [AArch64] Limit immediate offsets when folding instructions into addressing modes (#67345) · fe763d8a
  Momchil Velikov authored Sep 26, 2023
  fe763d8a
Sep 25, 2023
- Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC. · 98e8f04c
  Simon Pilgrim authored Sep 25, 2023
  
  98e8f04c
- [MachineSink][AArch64] Sink instruction copies when they can replace copy into... · c649fd34
  Momchil Velikov authored Sep 25, 2023
  c649fd34
Sep 23, 2023
- Reapply "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre" · bcc5b48b
  Zhuojia Shen authored Sep 22, 2023
  bcc5b48b
Sep 22, 2023
- [AArch64] Move PAuth codegen down the machine pipeline · eb02ee44
  Anatoly Trosinenko authored Sep 22, 2023
  eb02ee44
- [NFC][CodeGen] Create method to clear registers (#66958) · 9e41c284
  Bill Wendling authored Sep 21, 2023
  9e41c284
Sep 21, 2023
- [AArch64] Separate PNR into its own Register Class (#65306) · b967f3a1
  Matthew Devereau authored Sep 21, 2023
  b967f3a1
- [AArch64] Correctly determine if {ADD,SUB}{W,X}rs instructions are cheap · 0eb0a65d
  Momchil Velikov authored Sep 21, 2023
  0eb0a65d
- [AArch64] Refactor AArch64InstrInfo::isAsCheapAsAMove (NFC) · ededcb00
  Momchil Velikov authored Sep 21, 2023
  ededcb00
Sep 19, 2023
- [AArch64] Move LDR_PXI from isStoreToStackSlot to isLoadFromStackSlot (#65658) · 9a04bc4c
  weiguozhi authored Sep 18, 2023
  9a04bc4c