Commits · fcd545863d27148f26a3ef98bd20501a4df48ec5 · Roger Ferrer / llvm-epi · GitLab

Oct 21, 2022
- [AArch64] Add SVE2.1 target feature for Armv9-A 2022 Architecture Extension · fcd54586
  David Sherwood authored Oct 18, 2022
  fcd54586
- [AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector · 3bee2fb2
  Caroline Concatto authored Oct 21, 2022
  3bee2fb2
- [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers · 830b5e82
  Caroline Concatto authored Oct 20, 2022
  830b5e82
- [AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources · fc0cde8a
  Caroline Concatto authored Oct 20, 2022
  fc0cde8a
- [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers · 1e4f82c2
  Caroline Concatto authored Oct 17, 2022
  1e4f82c2
- [MachineCombiner][RISCV] Relax optimization level requirement · 14a5b9cd
  Anton Sidorenko authored Oct 19, 2022
  14a5b9cd
- [X86] Fold scalar_to_vector(i64 zext(x)) -> bitcast(vzext_movl(scalar_to_vector(i32 x))) · 5ca77541
  Simon Pilgrim authored Oct 21, 2022
  5ca77541
- [LoongArch] Stack realignment support · daf067da
  wanglei authored Oct 21, 2022
  daf067da
- [ARM] Fix the type for v4f16 duplane · fb76d2ce
  David Green authored Oct 21, 2022
  fb76d2ce
- [LoongArch] Modify ParserMethod for the simm26_b operand type · 67902920
  wanglei authored Oct 21, 2022
  67902920
- [AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR · 1809414f
  Pierre van Houtryve authored Oct 19, 2022
  1809414f
- [AMDGPU][DAG] Fix trunc/shift combine condition · 824dd811
  Pierre van Houtryve authored Oct 17, 2022
  824dd811
- [LoongArch] Report error in AsmParser when rd == rk or rd == rj for AM* instructions · c98add7a
  Weining Lu authored Oct 21, 2022
  c98add7a
- [X86][AVX] Eliminate redundant movzbl instruction. · 889911ec
  Luo, Yuanke authored Oct 19, 2022
  889911ec
- [Arm64EC] Refer to dllimport'ed functions correctly. · a6ac9683
  Eli Friedman authored Oct 20, 2022
  a6ac9683
Oct 20, 2022
- [MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with... · 2c82080f
  Craig Topper authored Oct 20, 2022
  2c82080f
- Revert "[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers" · 98954470
  Caroline Concatto authored Oct 20, 2022
  98954470
- Revert "[AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources" · c05b1bde
  Caroline Concatto authored Oct 20, 2022
  c05b1bde
- [AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources · 3fee9358
  Caroline Concatto authored Oct 20, 2022
  3fee9358
- [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers · 4c490970
  Caroline Concatto authored Oct 17, 2022
  4c490970
- [AArch64] Fix scheduler crash in fusion code. · decb743e
  Eli Friedman authored Oct 20, 2022
  decb743e
- [AArch64]SME2 Multiple vector ternary int/float 2 and 4 registers · 9db12a45
  Caroline Concatto authored Oct 17, 2022
  9db12a45
- [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add · 74c2d4f6
  zhongyunde authored Oct 21, 2022
  74c2d4f6
- [RISCV] Remove EEW from some sched classes. · c66426f3
  Craig Topper authored Oct 20, 2022
  c66426f3
- [AArch64][SME] Remove get.pstatesm intrinsic. · 5e5baf91
  Sander de Smalen authored Oct 20, 2022
  5e5baf91
- [AMDGPU][MC][GFX11][NFC] Improve error message when a VOPD opcode is used with WS64 · db3e8582
  Dmitry Preobrazhensky authored Oct 20, 2022
  db3e8582
- [AMDGPU][MC] Correct v_cndmask operand types · ab045561
  Dmitry Preobrazhensky authored Oct 20, 2022
  ab045561
- [LoongArch] Fix 32-bit and 64-bit atomicrmw nand operand order errors · 0f4dc562
  gonglingqin authored Oct 20, 2022
  0f4dc562
- [X86][1/2] Support PREFETCHI instructions · 62ca7910
  Phoebe Wang authored Oct 20, 2022
  62ca7910
- [VE] Change the way to lower selectcc · 33dda45d
  Kazushi (Jam) Marukawa authored Oct 15, 2022
  33dda45d
Oct 19, 2022
- [Hexagon] Fix insertion point for pointer difference calculation · e5d9ab08
  Krzysztof Parzyszek authored Oct 19, 2022
  e5d9ab08
- [SPIR-V] Add get_image_num_mip_levels implementation · 6beac40f
  Michal Paszkowski authored Oct 19, 2022
  6beac40f
- [SPIR-V] Add atomic_init and fix atomic explicit lowering · 5fb4a051
  Michal Paszkowski authored Oct 19, 2022
  5fb4a051
- [DX] Fix missing preserved analysis · 607be386
  Chris Bieneman authored Oct 19, 2022
  607be386
- [AArch64] Fix minor issue introduced in D135950. · 36864d47
  Sander de Smalen authored Oct 19, 2022
  36864d47
- [AArch64] SME2 Single-multi vector ternary int/FP 2 and 4 registers · 2ecbe8c3
  Caroline Concatto authored Oct 03, 2022
  2ecbe8c3
- [AArch64][SME] Disable (SLP|Loop)Vectorizer when function may be executed in streaming mode. · 137459af
  Sander de Smalen authored Oct 19, 2022
  137459af
- [X86][RFC] Using `__bf16` for AVX512_BF16 intrinsics · bc181938
  Phoebe Wang authored Oct 19, 2022
  bc181938
- [AMDGPU] New helper function SIInsertWaitcnts::getVmemWaitEventType · f0ca946b
  Jay Foad authored Oct 19, 2022
  f0ca946b
- [AMDGPU] V_LDEXP_F16 encoding fix and doc update. · ad669856
  Joe Nash authored Oct 18, 2022
  ad669856