Commits · fe5599eac6a57ad5a354e3b6fec9e97332304bac · Roger Ferrer / llvm-epi · GitLab

Mar 20, 2020
- [llvm-ar] Use target triple to deduce archive kind for bitcode inputs · fe5599ea
  Pirama Arumuga Nainar authored Mar 19, 2020
  fe5599ea
- [InstCombine] Remove known bits constant folding · 2b52e4e6
  Nikita Popov authored Mar 07, 2020
  2b52e4e6
- [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile · 7899fe9d
  Fangrui Song authored Mar 19, 2020
  7899fe9d
- PR45181: Fix another invalid DIExpression combination · 63666533
  Vedant Kumar authored Mar 20, 2020
  63666533
- [InstCombine] Handle known shl nsw sign bit in SimplifyDemanded · 3205d1a8
  Nikita Popov authored Mar 20, 2020
  3205d1a8
- [DAGCombiner] Do not fold truncate(build_vector(..)) if it creates an illegal type · edcfb47f
  Pirama Arumuga Nainar authored Mar 17, 2020
  edcfb47f
- [PowerPC][AIX][NFC] Extend the test coverage of ByVal args. · 56122fcd
  Sean Fertile authored Mar 20, 2020
  56122fcd
- [InstCombine][X86] simplifyX86immShift - convert variable in-range vector... · 34659de5
  Simon Pilgrim authored Mar 20, 2020
  34659de5
- [ARM,MVE] Add ACLE intrinsics for the vaddv/vaddlv family. · 1adfa4c9
  Simon Tatham authored Mar 20, 2020
  1adfa4c9
- [ARM,MVE] Add ACLE intrinsics for the vminv/vmaxv family. · 45a9945b
  Simon Tatham authored Mar 20, 2020
  45a9945b
- [PowerPC][AIX][NFC] Add zero-sized by val params to cc test. · fc902cb6
  Sean Fertile authored Mar 20, 2020
  fc902cb6
- [DAGCombiner] Fix non-determinism problem related to argument evaluation order in visitFDIV · d168b777
  Bjorn Pettersson authored Mar 17, 2020
  d168b777
- AMDGPU: Add more tests for fshr · 53d6b156
  Matt Arsenault authored Mar 20, 2020
  
  53d6b156
- [AMDGPU] Enable divergence driven ISel for ADD/SUB i64 · 6e34e718
  alex-t authored Mar 19, 2020
  6e34e718
- [ARM,CDE] Implement CDE unpredicated Q-register intrinsics · 969034b8
  Mikhail Maltsev authored Mar 20, 2020
  969034b8
- [ARM,CDE] Implement CDE S and D-register intrinsics · d22e6617
  Mikhail Maltsev authored Mar 20, 2020
  d22e6617
- [ARM,CDE] Implement GPR CDE intrinsics · 7a85e358
  Mikhail Maltsev authored Mar 20, 2020
  7a85e358
- [DSE,MSSA] Precommit additional tests for D73763. · ece6cf0f
  Florian Hahn authored Mar 20, 2020
  
  ece6cf0f
- [ValueTracking] Add some initial isKnownNonZero DemandedElts support (PR36319) · 7f764fa1
  Simon Pilgrim authored Mar 20, 2020
  
  7f764fa1
- [InstCombine] Move test to instcombine; NFC · ce6c95aa
  Nikita Popov authored Mar 20, 2020
  ce6c95aa
- [ValueTracking] Add computeKnownBits DemandedElts support to shift instructions (PR36319) · c1efdbcb
  Simon Pilgrim authored Mar 20, 2020
  
  c1efdbcb
- [Tests] Regenerate some test checks; NFC · a09ff56b
  Nikita Popov authored Mar 20, 2020
  
  a09ff56b
- [llvm-readobj] Allow syms from all sections to match stack size entries · 86b093d1
  James Henderson authored Mar 18, 2020
  86b093d1
- [llvm-readobj][llvm-readelf][test] - Add a test to check how we dump relocation addends. · 63778bc6
  Georgii Rymar authored Mar 05, 2020
  63778bc6
- [ARM] Change VDUP type to i32 for MVE · b3499f57
  David Green authored Mar 20, 2020
  b3499f57
- [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w · 3c24aee7
  Roger Ferrer authored Mar 20, 2020
  3c24aee7
- [NFC][RISCV] Test for 0.0 fp immediate · ebb04e9c
  Roger Ferrer authored Mar 20, 2020
  ebb04e9c
- [InstCombine] Simplify calls with "returned" attribute · 03727687
  Nikita Popov authored Mar 07, 2020
  03727687
- [ARM] Extra MVE float loop tests. NFC · 9cf920e6
  David Green authored Mar 20, 2020
  
  9cf920e6
- [InstCombine] Don't replace musttail result based on known bits · 5c109671
  Nikita Popov authored Mar 19, 2020
  5c109671
- [DSE] Support traversing MemoryPhis. · 3a8372ed
  Florian Hahn authored Mar 20, 2020
  3a8372ed
- [AMDGPU] Reuse register during frame index elimination · 2cbb8c94
  Austin Kerbow authored Mar 18, 2020
  2cbb8c94
- [AMDGPU] Set the CostPerUse value for vgpr registers. · 728b878d
  cdevadas authored Mar 19, 2020
  728b878d
- Revert "Generate Callee Saved Register (CSR) related cfi directives like .cfi_restore." · a035726e
  Wei Mi authored Mar 19, 2020
  a035726e
- [Coroutines] Fix PR45130 · 032251e3
  Jun Ma authored Mar 18, 2020
  032251e3
- [WebAssembly] Support swiftself and swifterror for WebAssembly target · 08670d43
  Yuta Saito authored Mar 19, 2020
  08670d43
- [WebAssembly] SIMD integer abs instructions · 34db3c3a
  Thomas Lively authored Mar 18, 2020
  34db3c3a
- [WebAssembly] SIMD bitmask intrinsics and builtin functions · a3f974f3
  Thomas Lively authored Mar 18, 2020
  a3f974f3
- [GlobalISel] Port some basic shufflevector undef combines from the DAGCombiner · c9990846
  Jessica Paquette authored Mar 18, 2020
  c9990846
Mar 19, 2020
- [InstSimplify] Add some vector shift tests to show lack of DemandedElts support · 95b6f62e
  Simon Pilgrim authored Mar 19, 2020
  
  95b6f62e