Commits · 1fb90133681255d38eed5c75c0fb64c9b090a7f5 · Raul Torres / llvm-target-spread · GitLab

Jun 28, 2018
- AMDGPU: Error on calls from graphics shaders · 1fb90133
  Matt Arsenault authored Jun 28, 2018
  1fb90133
- AMDGPU: Fix AMDGPUCodeGenPrepare using uninitialized AMDGPUAS struct · 12269dda
  Matt Arsenault authored Jun 28, 2018
  12269dda
- AMDGPU: Fix assert on aggregate type kernel arguments · 513e0c0e
  Matt Arsenault authored Jun 28, 2018
  513e0c0e
Jun 27, 2018
- [AMDGPU] Convert rcp to rcp_iflag · 1a1687f1
  Stanislav Mekhanoshin authored Jun 27, 2018
  1a1687f1
- AMDGPU/NFC: Fix typo in comment · 30f03b3b
  Konstantin Zhuravlyov authored Jun 27, 2018
  30f03b3b
Jun 26, 2018
- AMDGPU: Silence unused warnings in waitcnt insertion pass in release build · 77747770
  Konstantin Zhuravlyov authored Jun 26, 2018
  77747770
- [AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic · dacda79e
  Stanislav Mekhanoshin authored Jun 26, 2018
  dacda79e
- AMDGPU: Add pass to lower kernel arguments to loads · 8c4a3523
  Matt Arsenault authored Jun 26, 2018
  8c4a3523
Jun 25, 2018
- AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr · b1cc4f52
  Matt Arsenault authored Jun 25, 2018
  b1cc4f52
- AMDGPU: Remove commented out code · 2811a20f
  Matt Arsenault authored Jun 25, 2018
  2811a20f
- AMDGPU/GlobalISel: Fix G_IMPLICIT_DEF for pointers · b3feccd7
  Matt Arsenault authored Jun 25, 2018
  b3feccd7
- AMDGPU: Respect align argument parameter · 73eeb42e
  Matt Arsenault authored Jun 25, 2018
  73eeb42e
Jun 23, 2018
- [AMDGPU] Update includes for intrinsic changes :( · fd7c9ab9
  Reid Kleckner authored Jun 23, 2018
  fd7c9ab9
- [IR] Split Intrinsics.inc into enums and implementations · f5890e4e
  Reid Kleckner authored Jun 23, 2018
  f5890e4e
Jun 22, 2018
- AMDGPU: Add patterns for i32/i64 local atomic load/store · 3f8e7a3d
  Matt Arsenault authored Jun 22, 2018
  3f8e7a3d
- AMDGPU/GlobalISel: Default to using TableGen'd instruction selector · 6af73076
  Tom Stellard authored Jun 22, 2018
  6af73076
- AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR · 26fac0f8
  Tom Stellard authored Jun 22, 2018
  26fac0f8
- AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP · 9a653571
  Tom Stellard authored Jun 22, 2018
  9a653571
- AMDGPU/GlobalISel: Implement select() for COPY · 7712ee88
  Tom Stellard authored Jun 22, 2018
  7712ee88
- AMDGPU/GlobalISel: Implement select() for G_IMPLICIT_DEF · 3f1c6fe1
  Tom Stellard authored Jun 21, 2018
  3f1c6fe1
Jun 21, 2018
- AMDGPU: Remove ability to reserve VGPRs for debugger · e004b3d9
  Konstantin Zhuravlyov authored Jun 21, 2018
  e004b3d9
- [AMDGPU] Update assembler for HSA Code Object v3 · 1e8c2c70
  Scott Linder authored Jun 21, 2018
  1e8c2c70
- [AMDGPU] Fix bug with tracking processed blocks in SIInsertWaitcnts · 5792dd0f
  Scott Linder authored Jun 21, 2018
  5792dd0f
- AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z · 766c77ef
  Konstantin Zhuravlyov authored Jun 21, 2018
  766c77ef
- AMDGPU: Remove redundant MIMG instruction variants · 15745ba5
  Nicolai Haehnle authored Jun 21, 2018
  15745ba5
- AMDGPU: Remove old-style image intrinsics · db6911a6
  Nicolai Haehnle authored Jun 21, 2018
  db6911a6
- AMDGPU: Select MIMG instructions manually in SITargetLowering · 7a9c03f4
  Nicolai Haehnle authored Jun 21, 2018
  7a9c03f4
- AMDGPU: Refactor MIMG instruction TableGen using generic tables · 0ab200b6
  Nicolai Haehnle authored Jun 21, 2018
  0ab200b6
- AMDGPU: Use generic tables instead of SearchableTable · e741d7e0
  Nicolai Haehnle authored Jun 21, 2018
  e741d7e0
- AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM) · 2367f035
  Nicolai Haehnle authored Jun 21, 2018
  2367f035
- AMDGPU: Add implicit def of SCC to kill and indirect pseudos · b3a9b685
  Nicolai Haehnle authored Jun 21, 2018
  b3a9b685
- AMDGPU: Turn D16 for MIMG instructions into a regular operand · f2674319
  Nicolai Haehnle authored Jun 21, 2018
  f2674319
Jun 20, 2018
- AMDGPU: Fix scalar_to_vector for v4i16/v4f16 · 5a4ec812
  Matt Arsenault authored Jun 20, 2018
  5a4ec812
- AMDGPU: Fix missing C++ mode comment · 3d06668a
  Matt Arsenault authored Jun 20, 2018
  3d06668a
Jun 16, 2018
- [AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc · 3b11794d
  Stanislav Mekhanoshin authored Jun 16, 2018
  3b11794d
Jun 15, 2018
- AMDGPU: Add combine for short vector extract_vector_elts · 63bc0e3c
  Matt Arsenault authored Jun 15, 2018
  63bc0e3c
- AMDGPU: Make v4i16/v4f16 legal · 02dc7e19
  Matt Arsenault authored Jun 15, 2018
  02dc7e19
- [AMDGPU] Recognize x & ~(-1 << y) pattern. · dec562c8
  Roman Lebedev authored Jun 15, 2018
  dec562c8
- [AMDGPU] Recognize x & ((1 << y) - 1) pattern. · 9c17dad8
  Roman Lebedev authored Jun 15, 2018
  9c17dad8
- [AMDGPU] Recognize x & (-1 >> (32 - y)) pattern. · aa8587d1
  Roman Lebedev authored Jun 15, 2018
  aa8587d1