Commits · 6452ba478638f1b40ff36727c766d7d16651d2b6 · Raul Torres / llvm-target-spread · GitLab

Mar 20, 2019
- [X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend. · 03675533
  Craig Topper authored Mar 20, 2019
  03675533
- [X86] Use getConstantOperandAPInt to detect out-of-range shifts. · 2acca37a
  Simon Pilgrim authored Mar 20, 2019
  2acca37a
- [X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI · 624f5def
  Andrea Di Biagio authored Mar 20, 2019
  624f5def
- [X86] Re-disable cmpxchg16b for 32-bit mode assembly parsing. · 97d104cb
  Craig Topper authored Mar 19, 2019
  97d104cb
Mar 19, 2019
- [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - handle repeated shift amounts · e744f513
  Simon Pilgrim authored Mar 19, 2019
  e744f513
- [NFC] Fix unused variable in release builds · f74d45a7
  Jordan Rupprecht authored Mar 19, 2019
  f74d45a7
- [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGBuilder::visitSelect · a56f2822
  Simon Pilgrim authored Mar 19, 2019
  a56f2822
Mar 18, 2019
- [X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode. · b24bdf62
  Craig Topper authored Mar 18, 2019
  b24bdf62
- [X86] Allow any 8-bit immediate to be used with BT/BTC/BTR/BTS not just sign... · e732bc6b
  Craig Topper authored Mar 18, 2019
  e732bc6b
- [X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be... · f086e562
  Craig Topper authored Mar 18, 2019
  f086e562
- [X86] Replace uses of i64immSExt32_su with i64relocImmSExt32_su. · 0b9c640f
  Craig Topper authored Mar 18, 2019
  0b9c640f
- [X86] Rename imm8_su/imm16_su/imm32_su to... · f07062a7
  Craig Topper authored Mar 18, 2019
  f07062a7
- [TargetLowering] Add code size information on isFPImmLegal. NFC · 664c1ef5
  Adhemerval Zanella authored Mar 18, 2019
  664c1ef5
- [X86] Remove the _alt forms of (V)CMP instructions. Use a combination of... · c2b35ebc
  Craig Topper authored Mar 18, 2019
  c2b35ebc
- [X86] Hopefully fix a tautological compare warning in printVecCompareInstr. · ba898da1
  Craig Topper authored Mar 18, 2019
  ba898da1
- [X86] Make ADD*_DB post-RA pseudos and expand them in expandPostRAPseudo. · b4c49255
  Craig Topper authored Mar 18, 2019
  b4c49255
- [X86] Add tab character to the custom printing of VPCMP and VPCOM instructions. · 860a2720
  Craig Topper authored Mar 18, 2019
  860a2720
Mar 17, 2019
- [X86] Merge printf32mem/printi32mem into a single printdwordmem. Do the same... · 04cc28fe
  Craig Topper authored Mar 17, 2019
  04cc28fe
- [X86] Remove the _alt forms of AVX512 VPCMP instructions. Use a combination of... · affead9a
  Craig Topper authored Mar 17, 2019
  affead9a
- [X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of... · 12509d87
  Craig Topper authored Mar 17, 2019
  12509d87
Mar 16, 2019
- [X86][SSE] Constant fold PEXTRB/PEXTRW/EXTRACT_VECTOR_ELT nodes. · f2c53b5d
  Simon Pilgrim authored Mar 16, 2019
  f2c53b5d
- [X86] Add SimplifyDemandedBitsForTargetNode support for PEXTRB/PEXTRW · 0f472e1d
  Simon Pilgrim authored Mar 16, 2019
  0f472e1d
Mar 15, 2019
- [X86] X86ISelLowering::combineSextInRegCmov(): also handle i8 CMOV's · 9f377906
  Roman Lebedev authored Mar 15, 2019
  9f377906
- [X86] Promote i8 CMOV's (PR40965) · b6e376dd
  Roman Lebedev authored Mar 15, 2019
  b6e376dd
- [X86] Strip the SAE bit from the rounding mode passed to the _RND opcodes. Use... · af856db9
  Craig Topper authored Mar 15, 2019
  af856db9
- [X86][SSE] Fold scalar_to_vector(i64 anyext(x)) -> bitcast(scalar_to_vector(i32 anyext(x))) · d33e62c8
  Simon Pilgrim authored Mar 15, 2019
  d33e62c8
- [X86][GlobalISEL] Support lowering aligned unordered atomics · d238bf78
  Philip Reames authored Mar 15, 2019
  d238bf78
- [X86] Add SimplifyDemandedBitsForTargetNode support for PINSRB/PINSRW · 65165d54
  Simon Pilgrim authored Mar 15, 2019
  65165d54
- [X86][SSE] Attempt to convert SSE shift-by-var to shift-by-imm. · 0ad17402
  Simon Pilgrim authored Mar 15, 2019
  0ad17402
Mar 14, 2019
- [X86] Fix the pattern changes from r356121 so that the ROR*r1/ROR*m1 pattern use the rotr opcode. · c747ac3f
  Craig Topper authored Mar 14, 2019
  c747ac3f
- [x86] prevent infinite looping from vselect commutation (PR41066) · 5d1df114
  Sanjay Patel authored Mar 14, 2019
  5d1df114
- [X86] Add patterns for rotr by immediate to fix PR41057. · 54a0b533
  Craig Topper authored Mar 14, 2019
  54a0b533
Mar 13, 2019
- [X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() · 84abec28
  Craig Topper authored Mar 13, 2019
  84abec28
- [X86][AVX] Add X86ISD::VTRUNC handling to SimplifyDemandedVectorEltsForTargetNode · bef4fe05
  Simon Pilgrim authored Mar 13, 2019
  bef4fe05
- [X86][AVX] Add combineConcatVectors support to improve subvector handling · d9aa879b
  Simon Pilgrim authored Mar 13, 2019
  d9aa879b
- [x86] limit extractelement of setcc to pre-legalization · 0a251e40
  Sanjay Patel authored Mar 13, 2019
  0a251e40
- Fix signed/unsigned mismatch warning. NFCI. · 0c1e5aac
  Simon Pilgrim authored Mar 13, 2019
  0c1e5aac
- [X86][AVX] lowerShuffleAsBroadcast - improve load folding by avoiding bitcasts · 7abbd703
  Simon Pilgrim authored Mar 13, 2019
  7abbd703
- [ELF] Fix GCC8 warnings about "fall through", NFCI · c64d73cc
  Jonas Hahnfeld authored Mar 13, 2019
  c64d73cc
- [X86] Enable printAliasInstr for the Intel assembly printer so that AAM and... · 750efba6
  Craig Topper authored Mar 13, 2019
  750efba6