Commits · 746da5fe2a407254753965473728ee574d1b906c · Raul Torres / llvm-target-spread · GitLab

Mar 12, 2015
- Remove the need to cache the subtarget in the ARM TargetRegisterInfo · 34085832
  Eric Christopher authored Mar 12, 2015
  34085832
Aug 13, 2014
- Canonicalize header guards into a common format. · a7c40ef0
  Benjamin Kramer authored Aug 13, 2014
  a7c40ef0
Mar 23, 2014
- Prune includes in ARM target. · a9253267
  Craig Topper authored Mar 22, 2014
  a9253267
Jun 07, 2013
- Don't cache the instruction and register info from the TargetMachine, because · f95178e6
  Bill Wendling authored Jun 07, 2013
  f95178e6
Mar 17, 2012
- Reorder includes to match coding standards. Fix an issue or two exposed by that. · 188ed9d5
  Craig Topper authored Mar 17, 2012
  188ed9d5
Feb 18, 2012
- Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... · b22310fd
  Jia Liu authored Feb 18, 2012
  b22310fd
Dec 20, 2011
- Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch · a379b181
  David Blaikie authored Dec 20, 2011
  a379b181
May 24, 2010
- Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums · 6c47d642
  Jakob Stoklund Olesen authored May 24, 2010
  6c47d642
May 15, 2010
- Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE · 8c2d062e
  Evan Cheng authored May 14, 2010
  8c2d062e
May 14, 2010
- Added a QQQQ register file to model 4-consecutive Q registers. · cd67c214
  Evan Cheng authored May 14, 2010
  cd67c214
May 06, 2010
- Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a... · 31cdcd46
  Evan Cheng authored May 06, 2010
  31cdcd46
- Revert r103156 since it was breaking the build bots. · 9feb1bb1
  Eric Christopher authored May 06, 2010
  9feb1bb1
- Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q... · 8f99a1c6
  Evan Cheng authored May 06, 2010
  8f99a1c6
Oct 07, 2009
- Add codegen support for NEON vld2 operations on quad registers. · e6b778d5
  Bob Wilson authored Oct 06, 2009
  e6b778d5
Jul 08, 2009
- Push methods into base class in preparation for sharing. · 9ca33e8a
  David Goodwin authored Jul 08, 2009
  9ca33e8a
- Start breaking out common base functionality for register info. · eebf5880
  David Goodwin authored Jul 08, 2009
  eebf5880
Jun 27, 2009
- Simplify a bit · 0f2158b3
  Anton Korobeynikov authored Jun 27, 2009
  0f2158b3
- ARM refactoring. Step 2: split RegisterInfo · a1b5b18b
  Anton Korobeynikov authored Jun 27, 2009
  a1b5b18b
Jun 18, 2009
- - Update register allocation hint after coalescing. This is done by the target... · 0e796035
  Evan Cheng authored Jun 18, 2009
  0e796035
Jun 15, 2009
- Part 1. · 1283c6a0
  Evan Cheng authored Jun 15, 2009
  1283c6a0
Apr 07, 2009
- PR2985 / <rdar://problem/6584986 > · fde2110a
  Jim Grosbach authored Apr 07, 2009
  fde2110a
Feb 13, 2009
- Remove refs to non-DebugLoc versions of BuildMI from ARM. · 7647da67
  Dale Johannesen authored Feb 13, 2009
  7647da67
Feb 06, 2009
- Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. · 066757ee
  Evan Cheng authored Feb 06, 2009
  066757ee
Nov 12, 2008
- Fix encoding of single-precision VFP registers. · a0e2f263
  Evan Cheng authored Nov 12, 2008
  a0e2f263
Mar 31, 2008
- Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. · ed6e34fe
  Evan Cheng authored Mar 31, 2008
  ed6e34fe
Feb 10, 2008
- Rename MRegisterInfo to TargetRegisterInfo. · 3a4be0fd
  Dan Gohman authored Feb 10, 2008
  3a4be0fd
Jan 07, 2008
- Move even more functionality from MRegisterInfo into TargetInstrInfo. · 2a3be7bb
  Owen Anderson authored Jan 07, 2008
  2a3be7bb
Jan 05, 2008
- Move some more functionality from MRegisterInfo to TargetInstrInfo. · 6bb0c526
  Owen Anderson authored Jan 04, 2008
  6bb0c526
Jan 01, 2008
- Move some more instruction creation methods from RegisterInfo into InstrInfo. · eee14601
  Owen Anderson authored Jan 01, 2008
  eee14601
Dec 29, 2007
- Remove attribution from file headers, per discussion on llvmdev. · f3ebc3f3
  Chris Lattner authored Dec 29, 2007
  f3ebc3f3
Dec 05, 2007
- Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether · bb263018
  Evan Cheng authored Dec 05, 2007
  bb263018
Dec 02, 2007
- Remove redundant foldMemoryOperand variants and other code clean up. · f45a1d62
  Evan Cheng authored Dec 02, 2007
  f45a1d62
Dec 01, 2007
- Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0. · 69fda0a7
  Evan Cheng authored Dec 01, 2007
  69fda0a7
Nov 13, 2007
- Add parameter to getDwarfRegNum to permit targets · 7a7085f6
  Dale Johannesen authored Nov 13, 2007
  7a7085f6
Nov 11, 2007
- Use TableGen to emit information for dwarf register numbers. · 4edfea43
  Anton Korobeynikov authored Nov 11, 2007
  4edfea43
Oct 19, 2007
- - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but... · 463e2ab0
  Evan Cheng authored Oct 18, 2007
  463e2ab0
Oct 18, 2007
- Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. · aa9a2256
  Evan Cheng authored Oct 18, 2007
  aa9a2256
Oct 05, 2007
- - Added a few target hooks to generate load / store instructions from / to any · f4cf5dcd
  Evan Cheng authored Oct 05, 2007
  f4cf5dcd
Sep 26, 2007
- Allow copyRegToReg to emit cross register classes copies. · c1e4e374
  Evan Cheng authored Sep 26, 2007
  c1e4e374
Aug 30, 2007
- Add a variant of foldMemoryOperand to fold any load / store, not just load /... · 9a25d98c
  Evan Cheng authored Aug 30, 2007
  9a25d98c