Commits · 9173b5a99daea1768adacefd690243522b567d1a · Raul Torres / llvm-target-spread · GitLab

Nov 04, 2020
- Revert "[NewPM] Add OptimizationLevel param to registerPipelineStartEPCallback" · 9173b5a9
  Arthur Eubanks authored Nov 04, 2020
  9173b5a9
- [NewPM] Add OptimizationLevel param to registerPipelineStartEPCallback · 7a83aa05
  Arthur Eubanks authored Nov 04, 2020
  7a83aa05
- [crashlog] Pass the debugger around instead of relying on lldb.debugger · c29c24be
  Jonas Devlieghere authored Nov 04, 2020
  c29c24be
- [flang][openacc] Lower update directive · b45ea445
  Valentin Clement authored Nov 04, 2020
  b45ea445
- Fix -Wsign-compare issue in MasmParser.cpp · e6cd3eff
  Eric Astor authored Nov 04, 2020
  
  e6cd3eff
- [ms] [llvm-ml] Lex MASM strings, including escaping · 07c4f1d1
  Eric Astor authored Nov 04, 2020
  07c4f1d1
- [SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL · c126eb75
  Cameron McInally authored Nov 04, 2020
  c126eb75
- [NFC] Use Register/MCRegister · 5dc47541
  Mircea Trofin authored Nov 03, 2020
  5dc47541
- [flang][openacc] Lower enter data directive · c71adeff
  Valentin Clement authored Nov 04, 2020
  c71adeff
- [lld][ELF][test] test LTO-removed symbols are not in symtab · 1f78ab0a
  Edd Dawson authored Nov 03, 2020
  1f78ab0a
- [libc++] Remove stray setting of use_system_cxx_lib left behind · 8e01749b
  Louis Dionne authored Nov 04, 2020
  
  8e01749b
- [libc++] Move availability-related Lit configuration to the DSL · 70eb30cc
  Louis Dionne authored Nov 04, 2020
  70eb30cc
- [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns. · cc3bf270
  Craig Topper authored Nov 04, 2020
  cc3bf270
- [flang][openacc] Lower exit data directive · 2e73a1f9
  Valentin Clement authored Nov 04, 2020
  2e73a1f9
- [MemorySSA] Use provided memory location even if instruction is call · 52b86d35
  Nikita Popov authored Oct 03, 2020
  52b86d35
- Add info about the cherry-picked commit and contributor · 09f2c92e
  Steven Wan authored Nov 04, 2020
  
  09f2c92e
- [PowerPC] Rename mftbl to mftb · 296c2f31
  Steven Wan authored Oct 15, 2020
  296c2f31
- [mlir][std] Add SignedCeilDivIOp and SignedFloorDivIOp with std to std... · 07957156
  Alexandre Eichenberger authored Nov 04, 2020
  07957156
- [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions. · d47300f5
  Craig Topper authored Nov 04, 2020
  d47300f5
- Basic: Split out DirectoryEntry.h, NFC · 77a9e0a4
  Duncan P. N. Exon Smith authored Oct 29, 2020
  77a9e0a4
- [DAGCombine] Fix bug in load scalarization · f99580c1
  Fraser Cormack authored Apr 21, 2020
  f99580c1
- [libc++] NFC: Remove trailing whitespace · 0df0d0fe
  Louis Dionne authored Nov 04, 2020
  
  0df0d0fe
- Refactor PyPrintAccumulatorm, PyFileAccumulator, and... · 5b29d26b
  Mehdi Amini authored Nov 04, 2020
  5b29d26b
- Move MlirStringCallback declaration from mlir-c/IR.h to mlir-c/Support.h (NFC) · bf5c8625
  Mehdi Amini authored Nov 04, 2020
  bf5c8625
- [OpenMP] target nested `use_device_ptr() if()` and is_device_ptr trigger asserts · d0d43b58
  cchen authored Nov 04, 2020
  d0d43b58
- [RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns. · 0122a4ea
  Craig Topper authored Nov 04, 2020
  0122a4ea
- [MLIR] Refactor memref type -> LLVM Type conversion · 8c2025cc
  Rahul Joshi authored Nov 04, 2020
  8c2025cc
- [MLIR] Remove NoSideEffect from std.global_memref op. · 63e72aa4
  Rahul Joshi authored Nov 04, 2020
  63e72aa4
- Start of an llvm.coro.async implementation · ea5989b4
  Arnold Schwaighofer authored Oct 21, 2020
  ea5989b4
- [mlir] Make linalg-bufferize a composable bufferization pass · eb8d386d
  Sean Silva authored Nov 02, 2020
  eb8d386d
- [mlir] Fix materializations for unranked tensors. · f556af96
  Sean Silva authored Nov 02, 2020
  f556af96
- [RISCV] Check all 64-bits of the mask in SelectRORIW. · 857563ea
  Craig Topper authored Nov 04, 2020
  857563ea
- Switch from C-style comments `/* ... */` to C++ style `//` (NFC) · c7994bd9
  Mehdi Amini authored Nov 04, 2020
  c7994bd9
- [UBSan] Cannot negate smallest negative signed integer · 900ec97b
  Christopher Tetreault authored Nov 04, 2020
  900ec97b
- [RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI · 3701e33a
  Craig Topper authored Nov 04, 2020
  3701e33a
- [AMDGPU] Resolve pseudo registers at encoding uses · 58adab34
  Joe Nash authored Nov 03, 2020
  58adab34
- Revert "[GlobalISel] GISelKnownBits::computeKnownBitsImpl - Replace... · bbeb0849
  Fangrui Song authored Nov 04, 2020
  bbeb0849
- [NewPM] Don't run before pass instrumentation on required passes · d8f531c4
  Arthur Eubanks authored Oct 31, 2020
  d8f531c4
- [AMDGPU] Fix iterating in SIFixSGPRCopies · 31a0b283
  Sebastian Neubauer authored Oct 29, 2020
  31a0b283
- [llvm-objcopy] Make --set-section-flags work with --add-section · ee142c49
  Fangrui Song authored Nov 04, 2020
  ee142c49