Commits · 9bc2c059c3796813995e662d4418e1abfa2f5d73 · Raul Torres / llvm-target-spread · GitLab

Jun 22, 2018
- [X86] Don't accept (%si,%bp) 16-bit address expressions. · 9bc2c059
  Craig Topper authored Jun 22, 2018
  9bc2c059
- [X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encoded without using a zero displacement. · c26c62e0
  Craig Topper authored Jun 22, 2018
  c26c62e0
- AMDHSA: Put old assembler docs back · dd6b05c3
  Konstantin Zhuravlyov authored Jun 22, 2018
  dd6b05c3
- [X86][SSE] Add sdiv by (nonuniform) minus one tests (PR37119) · 938dbe66
  Simon Pilgrim authored Jun 22, 2018
  938dbe66
- [X86][AsmParser] Check for invalid 16-bit base register in Intel syntax. · cd18bb52
  Craig Topper authored Jun 22, 2018
  cd18bb52
- [X86] Don't allow ESP/RSP to be used as an index register in assembly. · 22d1db12
  Craig Topper authored Jun 22, 2018
  22d1db12
- [LoopUnswitch]Fix comparison for DomTree updates. · bee50036
  Alina Sbirlea authored Jun 22, 2018
  bee50036
- [llvm-mca] Remove redundant call. NFC · 1fa58109
  Andrea Di Biagio authored Jun 22, 2018
  1fa58109
- [X86] Add a test to show missed opportunity to generate vfnmadd · f9972338
  Easwaran Raman authored Jun 22, 2018
  f9972338
- Initialize LiveRegs once in BranchFolder::mergeCommonTails · 358a916a
  Krzysztof Parzyszek authored Jun 22, 2018
  358a916a
- [SLPVectorizer] Support alternate opcodes in tryToVectorizeList · 9d3ef8ee
  Simon Pilgrim authored Jun 22, 2018
  9d3ef8ee
- [llvm-mca] Set the operand ID for implicit register reads/writes. NFC · 21f0fdb2
  Andrea Di Biagio authored Jun 22, 2018
  21f0fdb2
- [llvm-mca] Introduce a sequential container of Stages · 43de6db2
  Matt Davis authored Jun 22, 2018
  43de6db2
- [SLPVectorizer] reorderAltShuffleOperands should just take InstructionsState. NFCI. · 213cb1b8
  Simon Pilgrim authored Jun 22, 2018
  213cb1b8
- Fix test again, try to keep all targets happy · 9b9e25d3
  Paul Robinson authored Jun 22, 2018
  9b9e25d3
- Fix test, nop is not always 1 byte · 6c434880
  Paul Robinson authored Jun 22, 2018
  6c434880
- [DWARFv5] Allow ".loc 0" to refer to the root file. · 11539b09
  Paul Robinson authored Jun 22, 2018
  11539b09
- [SLPVectorizer] Relax alternate opcodes to accept any BinaryOperator pair · 1e564504
  Simon Pilgrim authored Jun 22, 2018
  1e564504
- [SLPVectorizer][X86] Add alternate opcode tests for simple build vector cases · 229a7812
  Simon Pilgrim authored Jun 22, 2018
  229a7812
- [InstCombine] add shuffle+binops test from PR37806; NFC · c2b37f73
  Sanjay Patel authored Jun 22, 2018
  c2b37f73
- [InstCombine] add tests for shuffle-with-different-binops; NFC · cfd9da03
  Sanjay Patel authored Jun 22, 2018
  cfd9da03
- [InstCombine] rearrange shuffle-of-binops logic; NFC · a52963b4
  Sanjay Patel authored Jun 22, 2018
  a52963b4
- [X86] Regenerate tests to include fma comments · 234a6f68
  Simon Pilgrim authored Jun 22, 2018
  234a6f68
- [X86] Add notes to a few intrinsics · 4cd698b0
  Gabor Buella authored Jun 22, 2018
  4cd698b0
- Recommit r335333 "[MC] - Add .stack_size sections into groups and link them with .text" · dcf59c54
  George Rimar authored Jun 22, 2018
  dcf59c54
- [IR] Use Instruction::isBinaryOp helper instead of raw enum range tests. NFCI. · e0a6eb1f
  Simon Pilgrim authored Jun 22, 2018
  e0a6eb1f
- Revert r335332 "[MC] - Add .stack_size sections into groups and link them with .text" · 6d448da1
  George Rimar authored Jun 22, 2018
  6d448da1
- [MC] - Add .stack_size sections into groups and link them with .text · e14485a0
  George Rimar authored Jun 22, 2018
  e14485a0
- Recommit of r335326, with the test fixed that I missed. · 1043dffb
  Sjoerd Meijer authored Jun 22, 2018
  1043dffb
- [CostModel][AArch64] Add some initial costs for SK_Select and SK_PermuteSingleSrc · 9c8f9374
  Simon Pilgrim authored Jun 22, 2018
  9c8f9374
- Reverting r335326 while I look at the test failure · 7ee5b090
  Sjoerd Meijer authored Jun 22, 2018
  7ee5b090
- Revert r335324 due to a builtbot failure · 6d711ca1
  Eugene Leviant authored Jun 22, 2018
  6d711ca1
- [ARM] ARMv6m and v8m.baseline strict align · 8d2f1565
  Sjoerd Meijer authored Jun 22, 2018
  8d2f1565
- AMDGPU: Add patterns for i32/i64 local atomic load/store · 3f8e7a3d
  Matt Arsenault authored Jun 22, 2018
  3f8e7a3d
- [Evaluator] Improve evaluation of call instruction · ea19c947
  Eugene Leviant authored Jun 22, 2018
  ea19c947
- [X86] Changing the check for valid inputs in combineScalarToVector · 09635620
  Mikhail Dvoretckii authored Jun 22, 2018
  09635620
- Revert r335306 (and r335314) - the Call Graph Profile pass. · aa5f4d2e
  Chandler Carruth authored Jun 22, 2018
  aa5f4d2e
- AMDGPU/GlobalISel: Default to using TableGen'd instruction selector · 6af73076
  Tom Stellard authored Jun 22, 2018
  6af73076
- AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR · 26fac0f8
  Tom Stellard authored Jun 22, 2018
  26fac0f8
- [LegacyPM] Fix PR37888 by teaching the legacy loop pass manager how to · fe70b29c
  Chandler Carruth authored Jun 22, 2018
  fe70b29c