If the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast.

getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements.

I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win.

Differential Revision: https://reviews.llvm.org/D84441

This patch makes the check lines stricter.

Normally, we use yaml::Hex* to describe the length, offsets,
address/segment size. NFC.

Some buildbots require explicit clangdSupport dependency:

http://lab.llvm.org:8011/builders/llvm-avr-linux/builds/3996/steps/build%20stage%201/logs/stdio

Conversion of `spv.BranchConditional` now supports branch weights
that are mapped to weights vector in `llvm.cond_br`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D84657

Summary:
It returned an invalid location in case of a constrained-parameter
with no explicit arguments.

Reviewers: hokein

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D84613

...which is set based on HAVE_RPC_XDR_H.  At least Fedora 32 does not have a
/usr/include/rpc/xdr.h, so failed this test introduced with
<https://reviews.llvm.org/D83358> "[Sanitizers] Add interceptor for
xdrrec_create".

Differential Revision: https://reviews.llvm.org/D84740

Added a check for 'Function' storage class in `spv.globalVariable`
verifier since it only can be used with `spv.Variable`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D84731

This patch adds support of Volatile and Nontemporal
memory accesses to `spv.Load` and `spv.Store`. These attributes are
modelled with a `volatile` and `nontemporal` flags.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D84739

Function void run() on line 286 overrides a virtual function on line 92 of
clang-tools-extra/clangd/index/dex/dexp/Dexp.cpp.  Not marking it override will
cause a build failure when we use -Werror (every warning is treated as an error).

Reviewed By: kbobyrev (Kirill Bobyrev)

Differential Revision: https://reviews.llvm.org/D84794

The test output files whose atime is altered in the test were getting
accessed by Spotlight indexing on macOS, causing them to get an updated
atime and leading to the test not behaving as expected.

Reviewed By: jhenderson, steven_wu

Differential Revision: https://reviews.llvm.org/D84700

This patch corrects the order of operands in the pattern that lowers fshl
in Hexagon.

This patch addresses comments in D84640 (https://reviews.llvm.org/D84640#2178475).

Noticed by Jon Roelofs in https://reviews.llvm.org/D73151#2180499

We can implement find_first_unset_in() in the same function
if every BitWord we use is first flipped.

Differential Revision: https://reviews.llvm.org/D84717

It's possible to have terminator instructions after a write to exec,
so skip over them to find it.

This introduces the same bug llvm.amdgcn.s.setreg has where if the
user specified an immediate outside of the valid 16-bit range, it will
select into a verifier error.

- Add getArgumentTypes() to Region (missed from before)
- Adopt Region argument API in `hasMultiplyAddBody`
- Fix 2 typos in comments

Differential Revision: https://reviews.llvm.org/D84807

Instead, pattern match extends of extract_subvectors to generate
widening operations. Since extract_subvector is not a legal node, this
is implemented via a custom combine that recognizes extract_subvector
nodes before they are legalized. The combine produces custom ISD nodes
that are later pattern matched directly, just like the intrinsic was.

Also removes the clang builtins for these operations since the
instructions can now be generated from portable code sequences.

Differential Revision: https://reviews.llvm.org/D84556

We already had CMPXCH8B feature on this CPU for the frontend so
this doesn't have much effect.

The FeatureSlowUAMem16 only matters if someone compiles with
-march=lakemont -msse which doesn't make sense, but is consistent
with all our pre-sse4.2 CPUs. Maybe the feature flag should be
FeatureFastUAMem16 and set on the newer CPUs instead.

Currently GlobalISel doesn't force all VGPR phi operands to VGPRs, so
this hit a case where it was queried with a VGPR and SGPR. This could
arguably be a verifier error, but it's currently not.

Add wrapper classes to to access record's fields. This makes it easier to
pass record information to the diverse functions for code generation.

Reviewed By: jdenny

Differential Revision: https://reviews.llvm.org/D84612

Rather than expanding truncating stores so that vectors are stored one
lane at a time, lower them to a sequence of instructions using
narrowing operations instead, when possible. Since the narrowing
operations have saturating semantics, but truncating stores require
truncation, mask the stored value to manually truncate it before
narrowing. Also, since narrowing is a binary operation, pass in the
original vector as the unused second argument.

Differential Revision: https://reviews.llvm.org/D84377

GlobalISel let through a call to null, which would then fold into the
source operand like any other inline immediate. The SelectionDAG
lowering deletes calls to null and undef as a workaround from before
calls were supported. We should probably drop the special handling
case in the DAG lowering now, since the middle end optimizers delete
null calls anyway.

Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D84799

This reverts commit 3c3faae4.

It breaks a number of bots.

This reverts commit 2cb926a4.

It depends on 3c3faae4, which is being
reverted.

This would stop on the first in reverse order, failing the verifier if
there were more earlier in the block.

[NFC][OpenMP] Renamed all variable and function names in `target` to conform with LLVM code standard

This patch only touched variables and functions in `target`.

Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D84797

This needs an implicit def of the super-register in case one of the
lanes isn't defined, similar to copyPhysReg (or the not-VGPR spill
case below). This showed up in GlobalISel testing since it currently
doesn't fold out many undef instructions.

These should probably be inferred from the function on parse, but the
target specific infrastructure currently does not give you a way to do
this. SILowerSGPRSpills early exits without this reporting spills,
which makes it difficult to write a MIR test for.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D84697

This will fix the integration test which is failing currently.