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  1. Sep 21, 2021
    • Kunwar Shaanjeet Singh Grover's avatar
      [MLIR] Add mergeLocalIds and mergeSymbolIds · 0d12c991
      Kunwar Shaanjeet Singh Grover authored
      This patch adds mergeLocalIds andmergeSymbolIds as public functions
      for FlatAffineConstraints and FlatAffineValueConstraints respectively.
      
      mergeLocalIds is also required to support divisions in intersection,
      subtraction, equality checks, and complement for PresburgerSet.
      
      This patch is part of a series of patches aimed at generalizing affine
      dependence analysis.
      
      Reviewed By: bondhugula
      
      Differential Revision: https://reviews.llvm.org/D110045
      0d12c991
    • Nathan Ridge's avatar
      [clangd] Deduplicate inlay hints · d87d1aa0
      Nathan Ridge authored
      Duplicates can sometimes appear due to e.g. explicit template
      instantiations
      
      Differential Revision: https://reviews.llvm.org/D110051
      d87d1aa0
    • Amara Emerson's avatar
      [GlobalISel][Legalizer] Use ArtifactValueFinder first for unmerge combines before trying others. · cc65e08f
      Amara Emerson authored
      This is motivated by an pathological compile time issue during unmerge combining.
      
      We should be able to use the AVF to do simplification. However AMDGPU
      has a lot of codegen changes which I'm not sure how to evaluate.
      
      Differential Revision: https://reviews.llvm.org/D109748
      cc65e08f
    • Evgeniy Brevnov's avatar
      [DSE][NFC] Rename Later->Killing, Earlier->Dead · 129cf336
      Evgeniy Brevnov authored
      First (and biggest) change is to use "Killing/Dead" in place of "Later/Earlier" base for names in DSE. For example, [Maybe]DeadLoc - is a location killed by KillingI instruction. I believe such names are more descriptive and easy to understand than current ones.
      
      Second, there are inconsistencies in naming where different names are used for the same thing. Fixed that too.
      
      Third, reordered parameters of isPartialOverwrite, tryToMergePartialOverlappingStores, isOverwrite to make them consistent between each other. This greatly reduces potential mistakes.
      
      Reviewed By: fhahn
      
      Differential Revision: https://reviews.llvm.org/D106947
      129cf336
    • Amara Emerson's avatar
      [GlobalISel][Legalizer] Don't use eraseFromParentAndMarkDBGValuesForRemoval() for some artifacts. · 7091a7f7
      Amara Emerson authored
      For artifacts excluding G_TRUNC/G_SEXT, which have IR counterparts, we don't
      seem to have debug users of defs. However, in the legalizer we're always calling
      MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() which is expensive.
      In some rare cases, this contributes significantly to unreasonably long compile
      times when we have lots of artifact combiner activity.
      
      To verify this, I added asserts to that function when it actually replaced a debug
      use operand with undef for these artifacts. On CTMark with both -O0 and -Os and
      debug info enabled, I didn't see a single case where it triggered.
      
      In my measurements I saw around a 0.5% geomean compile-time improvement on -g -O0
      for AArch64 with this change.
      
      Differential Revision: https://reviews.llvm.org/D109750
      7091a7f7
    • Max Kazantsev's avatar
      [SCEV] Generalize implication when signedness of FoundPred doesn't matter · 2c7d5fbc
      Max Kazantsev authored
      The implication logic for two values that are both negative or non-negative
      says that it doesn't matter whether their predicate is signed and unsigned,
      but only flips unsigned into signed for further inference. This patch adds
      support for flipping a signed predicate into unsigned as well.
      
      Differential Revision: https://reviews.llvm.org/D109959
      Reviewed By: nikic
      2c7d5fbc
    • Yonghong Song's avatar
      BPF: make 32bit register spill with 64bit alignment · ea72b031
      Yonghong Song authored
      In llvm, for non-alu32 mode, the stack alignment is 64bit so only one
      64bit spill per 64bit slot. For alu32 mode, the stack alignment
      is 32bit, so it is possible to have two 32bit spills per
      64bit slot.
      
      Currently, bpf kernel verifier does not preserve register states
      for 32bit spills. That is, one 32bit register may hold a constant
      value or a bounded range before spill. After reload from the
      stack, the information is lost and sometimes this may cause
      verifier failure. For 64bit register spill, the verifier
      indeed tries to preserve the register state for reloading.
      
      The current verifier can be modestly changed to handle one
      32bit spill per 64bit stack slot with state-preserving reload.
      Handling two 32bit spills per 64bit stack slot will require
      substantial changes.
      
      This patch changes stack alignment for alu32 to be 64bit.
      This way, for any 64bit slot in alu32 mode, only one
      32bit or 64bit register values can be saved. Together
      with previous-mentioned verifier enhancement, 32bit
      spill can be handled with state preserving.
      
      Note that llvm stack slot coallescing
      seems only doing adjacent packing which may leave some holes
      in the stack. For example,
         stack slot 8   <== 8 bytes
         stack slot 4   <== 8 bytes with 4 byte hole
         stack slot 8   <== 8 bytes
         stack slot 4   <== 4 bytes
      
      Differential Revision: https://reviews.llvm.org/D109073
      ea72b031
    • Chris Lattner's avatar
      [OpAsmParser] Add a parseCommaSeparatedList helper and beef up Delimeter. · 58abc8c3
      Chris Lattner authored
      Lots of custom ops have hand-rolled comma-delimited parsing loops, as does
      the MLIR parser itself.  Provides a standard interface for doing this that
      is less error prone and less boilerplate.
      
      While here, extend Delimiter to support <> and {} delimited sequences as
      well (I have a use for <> in CIRCT specifically).
      
      Differential Revision: https://reviews.llvm.org/D110122
      58abc8c3
    • Max Kazantsev's avatar
      [SimplifyCFG] Redirect switch cases that lead to UB into an unreachable block · 073b254c
      Max Kazantsev authored
      When following a case of a switch instruction is guaranteed to lead to
      UB, we can safely break these edges and redirect those cases into a newly
      created unreachable block. As result, CFG will become simpler and we can
      remove some of Phi inputs to make further analyzes easier.
      
      Patch by Dmitry Bakunevich!
      
      Differential Revision: https://reviews.llvm.org/D109428
      Reviewed By: lebedev.ri
      073b254c
    • Michael Kruse's avatar
      [Polly] Don't generate inter-iteration noalias metadata. · cad9f98a
      Michael Kruse authored
      This metadata was intended to mark all accesses within an iteration to be pairwise non-aliasing, in this case because every memory of a base pointer is touched (read or write) at most once. This is typical for 'sweeps' over all data. The stated motivation from D30606 is to ensure that unrolled iterations are considered non-aliasing.
      
      Rhe implemention had multiple issues:
      
       * The structure of the noalias metadata was malformed. D110026 added check in the verifier for this metadata, and the tests were failing since then.
      
       * This is not true for the outer loops of the BLIS matrix multiplication, where it was being inserted. Each element of A, B, C is accessed multiple times, as often as the loop not used as an index is iterating.
      
       * Scopes were added to SecondLevelOtherAliasScopeList (used for the !noalias scop list) on-the-fly when another SCEV was seen. This meant that previously visited instructions would not be updated with alias scopes that are only seen later, missing out those SCEVs they should not be aliasing with.
      
       * Since the !noalias scope list would ideally consists of all other SCEV for this base pointer, we might run quickly into scalability issues. Especially after unrolling there would probably at least once SCEV per instruction and unroll instance.
      
       * The inter-iteration noalias base pointer was not removed after leaving the loop marked with it, effectively marking everything after it to noalias as well.
      
      A solution I considered was to mark each instruction as non-aliasing with its own scope. The instruction itself would obviously alias itself, but such construction might also be considered invalid. Duplicating the instruction (e.g. due to speculation) would mark the instruction non-aliasing with its clone. I don't want to go into this territory, especially since the original motivation of determining unrolled instances as noalias based on SCEV is the what scev-aa does as well.
      
      This effectively reverts D30606 and D35761.
      cad9f98a
    • Max Kazantsev's avatar
    • Kazu Hirata's avatar
      [llvm] Use make_early_inc_range (NFC) · 85b4b21c
      Kazu Hirata authored
      85b4b21c
    • River Riddle's avatar
      [mlir] Refactor ElementsAttr into an AttrInterface · d80d3a35
      River Riddle authored
      This revision refactors ElementsAttr into an Attribute Interface.
      This enables a common interface with which to interact with
      element attributes, without needing to modify the builtin
      dialect. It also removes a majority (if not all?) of the need for
      the current OpaqueElementsAttr, which was originally intended as
      a way to opaquely represent data that was not representable by
      the other builtin constructs.
      
      The new ElementsAttr interface not only allows for users to
      natively represent their data in the way that best suits them,
      it also allows for efficient opaque access and iteration of the
      underlying data. Attributes using the ElementsAttr interface
      can directly expose support for interacting with the held
      elements using any C++ data type they claim to support. For
      example, DenseIntOrFpElementsAttr supports iteration using
      various native C++ integer/float data types, as well as
      APInt/APFloat, and more. ElementsAttr instances that refer to
      DenseIntOrFpElementsAttr can use all of these data types for
      iteration:
      
      ```c++
      DenseIntOrFpElementsAttr intElementsAttr = ...;
      
      ElementsAttr attr = intElementsAttr;
      for (uint64_t value : attr.getValues<uint64_t>())
        ...;
      for (APInt value : attr.getValues<APInt>())
        ...;
      for (IntegerAttr value : attr.getValues<IntegerAttr>())
        ...;
      ```
      
      ElementsAttr also supports failable range/iterator access,
      allowing for selective code paths depending on data type
      support:
      
      ```c++
      ElementsAttr attr = ...;
      if (auto range = attr.tryGetValues<uint64_t>()) {
        for (uint64_t value : *range)
          ...;
      }
      ```
      
      Differential Revision: https://reviews.llvm.org/D109190
      d80d3a35
    • River Riddle's avatar
      [mlir] Add value_begin/value_end methods to DenseElementsAttr · 0cb5d7fc
      River Riddle authored
      Currently DenseElementsAttr only exposes the ability to get the full range of values for a given type T, but there are many situations where we just want the beginning/end iterator. This revision adds proper value_begin/value_end methods for all of the supported T types, and also cleans up a bit of the interface.
      
      Differential Revision: https://reviews.llvm.org/D104173
      0cb5d7fc
    • River Riddle's avatar
      [mlir] Tighten verification of SparseElementsAttr · 4f21152a
      River Riddle authored
      SparseElementsAttr currently does not perform any verfication on construction, with the only verification existing within the parser. This revision moves the parser verification to SparseElementsAttr, and also adds additional verification for when a sparse index is not valid.
      
      Differential Revision: https://reviews.llvm.org/D109189
      4f21152a
    • Stella Laurenzo's avatar
      [mlir][python] Forward _OperationBase _CAPIPtr to the Operation. · 1fb2e842
      Stella Laurenzo authored
      * ODS generated operations extend _OperationBase and without this, cannot be marshalled to CAPI functions.
      * No test case updates: this kind of interop is quite hard to verify with in-tree tests.
      
      Differential Revision: https://reviews.llvm.org/D110030
      1fb2e842
    • Usman Nadeem's avatar
      [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses · f417d9d8
      Usman Nadeem authored
      Differential Revision: https://reviews.llvm.org/D109808
      
      Change-Id: I1a10d2bc33acbe0ea353c6cb3d077851391fe73e
      f417d9d8
    • Nico Weber's avatar
      60ab6861
    • Nico Weber's avatar
      bde305ba
    • Chia-hung Duan's avatar
      [mlir-tblgen] Add DagNode StaticMatcher. · bb250606
      Chia-hung Duan authored
      Some patterns may share the common DAG structures. Generate a static
      function to do the match logic to reduce the binary size.
      
      Reviewed By: jpienaar
      
      Differential Revision: https://reviews.llvm.org/D105797
      bb250606
    • Mehdi Amini's avatar
      Update MLIR generate-test-checks.py to add the notice from the source into the generated file · 4e7c0a37
      Mehdi Amini authored
      Folks may not read the source of the tool and miss these instructions.
      
      Differential Revision: https://reviews.llvm.org/D110082
      4e7c0a37
    • Amara Emerson's avatar
      [X86] Rename the X86WinAllocaExpander pass and related symbols to "DynAlloca". NFC. · 4ceea774
      Amara Emerson authored
      For x86 Darwin, we have a stack checking feature which re-uses some of this
      machinery around stack probing on Windows. Renaming this to be more appropriate
      for a generic feature.
      
      Differential Revision: https://reviews.llvm.org/D109993
      4ceea774
    • natashaknk's avatar
      [mlir][tosa] Add several binary elementwise to the list of broadcastable ops. · 38ff7e11
      natashaknk authored
      Reviewed By: rsuderman
      
      Differential Revision: https://reviews.llvm.org/D110096
      38ff7e11
    • Nico Weber's avatar
      [clang] Fix a few comment typos to cycle bots · f1191705
      Nico Weber authored
      f1191705
    • natashaknk's avatar
      [mlir][tosa] Remove the documentation requirement for elements of several... · 4edf46f7
      natashaknk authored
      [mlir][tosa] Remove the documentation requirement for elements of several binary elementwise ops to be of the same rank.
      
      Reviewed By: rsuderman
      
      Differential Revision: https://reviews.llvm.org/D110095
      4edf46f7
  2. Sep 20, 2021
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