If a section has been replaced (Sec != Sec->Repl) it is not Live.

llvm-svn: 320597

OpenMP 5.0 added support for `reduction` clause in target-based
directives. Patch adds this support to clang.

llvm-svn: 320596

llvm-svn: 320595

Summary:
See D40657 & D40679 for previous versions of this patch & description.

A couple of things were fixed here to have it not break some bots.
Weak symbols can't be used with `SANITIZER_GO` so the previous version was
breakin TsanGo. I set up some additional local tests and those pass now.

I changed the workaround for the glibc vDSO issue: `__progname` is initialized
after the vDSO and is actually public and of known type, unlike
`__vdso_clock_gettime`. This works better, and with all compilers.

The rest is the same.

Reviewers: alekseyshl

Reviewed By: alekseyshl

Subscribers: srhines, kubamracek, krytarowski, llvm-commits, #sanitizers

Differential Revision: https://reviews.llvm.org/D41121

llvm-svn: 320594

There are two /proc/cpuinfo layots in use for AArch64: old and new.
The old one has all 'processor : n' lines in one section, hence
checking for duplications does not make sense.

Differential Revision: https://reviews.llvm.org/D41000

llvm-svn: 320593

Summary:
getScudoChunk function is implicitly inlined for optimized builds on
clang, but not on gcc. It's a small enough function that it seems
sensible enough to just inline it by default.

Reviewers: cryptoad, alekseyshl

Reviewed By: cryptoad

Differential Revision: https://reviews.llvm.org/D41138

llvm-svn: 320592

Usages of it were giving compiler errors because of the missing
explicit conversion.

llvm-svn: 320591

The compiler may generate incorrect code if we try to capture the
variable in clause parsing mode.

llvm-svn: 320590

llvm-svn: 320589

llvm-svn: 320588

llvm-svn: 320587

llvm-svn: 320586

llvm-svn: 320585

The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431

llvm-svn: 320584

llvm-svn: 320583

llvm-svn: 320582

Add missing RDTSCP itinerary

llvm-svn: 320581

llvm-svn: 320580

llvm-svn: 320579

llvm-svn: 320578

llvm-svn: 320577

Reviewers: sammccall, ioeric, hokein

Reviewed By: sammccall

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D40486

llvm-svn: 320576

Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.

llvm-svn: 320575

otherwise we will copy an object.

llvm-svn: 320574

Differential Revision: https://reviews.llvm.org/D41109

llvm-svn: 320573

Differential Revision: https://reviews.llvm.org/D41110

llvm-svn: 320572

Differential Revision: https://reviews.llvm.org/D41112

llvm-svn: 320571

Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK

We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...

Differential Revision: https://reviews.llvm.org/D41119

llvm-svn: 320570

Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.

llvm-svn: 320569

OpenGL issues should be fixed by now.

llvm-svn: 320568

Add missing case that was not implemented yet.

Differential Revision: https://reviews.llvm.org/D38942

llvm-svn: 320567

Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only debug syntax is affected.

llvm-svn: 320566

[CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output

Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.

Only debug syntax is affected.

llvm-svn: 320565

Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41116

llvm-svn: 320564

Summary: ... in qualified code completion and decl lookup.

Reviewers: ilya-biryukov, arphaman

Reviewed By: ilya-biryukov

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D40562

llvm-svn: 320563

Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.

Differential revision: https://reviews.llvm.org/D40959

llvm-svn: 320562

Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.

To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.

The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).

The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.

Reviewers: zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41065

llvm-svn: 320561

When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.

llvm-svn: 320560

We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.

llvm-svn: 320559

Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.

llvm-svn: 320558