Commits · 3b77e2737c8545aa628e1d2cff5799db033f7081 · Lorenzo Albano / LLVM bpEVL · GitLab

Jul 26, 2021
- [SVE] Use reg+reg addressing mode for immediate offsets. · 3b77e273
  Paul Walker authored Jul 22, 2021
  3b77e273
- [AArch64][SVE] Break false dependencies for inactive lanes of unary operations · 81eafb8a
  Bradley Smith authored Jul 08, 2021
  81eafb8a
- AArch64: support i128 (& larger) returns in GlobalISel · a487a49a
  Tim Northover authored Jul 26, 2021
  
  a487a49a
- [AArch65][SVE] Remove vector_splice from AddedComplexity pattern · bf28111e
  Caroline Concatto authored Jul 26, 2021
  bf28111e
- [SVE][AArch64] Improve code generation for vector_splice for Imm > 0 · 0bfc26e3
  Caroline Concatto authored Jul 19, 2021
  0bfc26e3
- [AArch64][SVE] Improve code generation for vector_splice for Imm == -1 · 73e4e9cd
  Caroline Concatto authored Jul 06, 2021
  73e4e9cd
- [AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc() · e6ff9179
  Cullen Rhodes authored Jul 26, 2021
  e6ff9179
- [Analysis] Add simple cost model for strict (in-order) reductions · 0aff1798
  David Sherwood authored Jul 07, 2021
  0aff1798
Jul 25, 2021
- [AArch64] Fix Local Deallocation for Homogeneous Prolog/Epilog · 6530ea40
  Kyungwoo Lee authored Jul 25, 2021
  6530ea40
- [AArch64][GlobalISel] Widen non-pow-2 types for shifts before clamping. · acbc0c5f
  Amara Emerson authored Jul 24, 2021
  acbc0c5f
Jul 23, 2021
- [llvm][sve] Silence unused variable warning in Release builds. NFC · dd70cd08
  Benjamin Kramer authored Jul 23, 2021
  
  dd70cd08
- [llvm][sve] Lowering for VLS truncating stores · 1528a4d4
  David Truby authored Jul 12, 2021
  1528a4d4
- [AArch64] Add worst case shuffle costs · 38986c67
  David Green authored Jul 23, 2021
  38986c67
- [AArch64][AsmParser] NFC: when creating a token IsSuffix=false should be default · fde75500
  Cullen Rhodes authored Jul 23, 2021
  fde75500
- [NFC][asan] Always pass Dominator Trees into forAllReachableExits · 44ba8c69
  Vitaly Buka authored Jul 22, 2021
  
  44ba8c69
Jul 22, 2021
- [AArch64] Adjust the cost of integer sum reductions · c9cebda7
  David Green authored Jul 22, 2021
  c9cebda7
- [AArch64][SME] Improve diagnostic for vector select register · 00e87e1c
  Cullen Rhodes authored Jul 22, 2021
  00e87e1c
Jul 21, 2021
- [AArch64][GlobalISel] Change | -> || in an if · c75a2bbe
  Jessica Paquette authored Jul 21, 2021
  c75a2bbe
- [AArch64][GlobalISel] Widen s2 and s4 G_IMPLICIT_DEF + G_FREEZE · d0af732b
  Jessica Paquette authored Jul 20, 2021
  d0af732b
- [SelectionDAG] Fix the representation of ISD::STEP_VECTOR. · 0ca46a17
  Eli Friedman authored Jul 08, 2021
  0ca46a17
- [AArch64][SME] Support .arch and .arch_extension assembler directives · 008c755d
  Cullen Rhodes authored Jul 21, 2021
  008c755d
- AArch64: support 8 & 16-bit atomic operations in GlobalISel · 291e0daa
  Tim Northover authored Jul 21, 2021
  291e0daa
- [AArch64][SME] Add mova instructions · 2d80bbd9
  Cullen Rhodes authored Jul 21, 2021
  2d80bbd9
- [AArch64][SME] Add ldr and str instructions · 6c32cfe8
  Cullen Rhodes authored Jul 21, 2021
  6c32cfe8
- [AArch64][GlobalISel] Legalize ctpop for v2s64, v2s32, v4s32, v4s16, v8s16 · 75187aa3
  Jon Roelofs authored Jul 20, 2021
  75187aa3
Jul 20, 2021
- [AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics · 8f54ebd5
  Jessica Paquette authored Jul 19, 2021
  8f54ebd5
- [AArch64] Use the CMP_SWAP_128 variants added in 843c6140 . · 664a1fd9
  Eli Friedman authored Jul 20, 2021
  664a1fd9
- [AArch64] Delete unused Opcode after D106039 · 0c0549fb
  Fangrui Song authored Jul 20, 2021
  
  0c0549fb
- [AArch64] Fix i128 cmpxchg using ldxp/stxp. · 843c6140
  Eli Friedman authored Jul 20, 2021
  843c6140
- [AArch64][SVE] Move instcombine like transforms out of SVEIntrinsicOpts · 191f9fa5
  Bradley Smith authored Jul 13, 2021
  191f9fa5
- [AArch64][SVE][InstCombine] last{a,b} of a splat vector · eb1a5120
  Sander de Smalen authored Jul 19, 2021
  eb1a5120
- [AArch64][SME] Add system registers and related instructions · 15af3aaa
  Cullen Rhodes authored Jul 20, 2021
  15af3aaa
- [AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128. · 56a6686e
  Amara Emerson authored Jul 20, 2021
  56a6686e
- AArch64/GlobalISel: Preserve memory types · 30fa074c
  Matt Arsenault authored Jul 16, 2021
  
  30fa074c
Jul 19, 2021
- Revert "[llvm][sve] Lowering for VLS truncating stores" because it · fd972bb9
  Amy Huang authored Jul 19, 2021
  fd972bb9
- [ARM] Remove PromotedBitwiseVT for NEON types · 5561ad8b
  David Green authored Jul 19, 2021
  5561ad8b
- AArch64/GlobalISel: Cleanup unnecessary size checks in call lowering · e574fd9d
  Matt Arsenault authored Jul 16, 2021
  e574fd9d
- [NFC] [MTE] helper for stack tagging lifetimes. · d23f26f0
  Florian Mayer authored Jul 16, 2021
  d23f26f0
- [AArch64][SME] Add SVE2 instructions added in SME · f91eaa70
  Cullen Rhodes authored Jul 19, 2021
  f91eaa70
- [AArch64][SVE] Optimize bitcasts between unpacked half/i16 vectors. · 0ed05735
  Sander de Smalen authored Jul 19, 2021
  0ed05735