As outlined in the PR, we didn't ensure that displacements for DQ-Form
instructions are multiples of 16. Since the instruction encoding encodes
a quad-word displacement, a sub-16 byte displacement is meaningless and
ends up being encoded incorrectly.

Fixes https://bugs.llvm.org/show_bug.cgi?id=33671.

Differential Revision: https://reviews.llvm.org/D35007

llvm-svn: 307934

llvm-svn: 307929

Pass parameters properly in calls to such functions (pass all
floats in integer registers), and handle va_start properly (allocate
stack immediately below the arguments on the stack, to save the
register arguments into a single continuous array).

Differential Revision: https://reviews.llvm.org/D35006

llvm-svn: 307928

llvm-svn: 307925

Summary: Completes the set.

Reviewers: ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D35278

llvm-svn: 307922

This commit reapplies r307215 now that we found out and fixed
the cause of the cfi test failure (in r307871).

llvm-svn: 307920

The AsmParser mnemonic spell checker was introduced in r307148 and enabled only
for ARM. This patch enables it for AArch64.

Differential Revision: https://reviews.llvm.org/D35357

llvm-svn: 307918

The feature will be used properly once assembler/disassembler support
begins to land.

llvm-svn: 307917

This patch is a follow-up to r305893 and adds preliminary support for the
fetch_sub and fetch_and operations.

llvm-svn: 307913

Summary:
When we runtime unroll with multiple exit blocks, we also need to update the
immediate dominators of the immediate successors of the exit blocks.

Reviewers: reames, mkuper, mzolotukhin, apilipenko

Reviewed by: mzolotukhin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35304

llvm-svn: 307909

For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC,
get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs.

For MIPS, only the DSP ASE has a carry flag, so in the general case it is not
useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes.

Also improve the generation code in such cases for targets with
TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the
comparison node rather than using it in selects. Similarly for ISD::SUBE /
ISD::SUBC.

Address optimization breakage by moving the generation of MIPS specific integer
multiply-accumulate nodes to before legalization.

This revolves PR32713 and PR33424.

Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue!

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D33494

The previous version of this patch was too aggressive in producing fused
integer multiple-addition instructions.

llvm-svn: 307906

This boils down to not crashing in reg bank select due to the lack of
register operands on this instruction, and adding some tests. The
instruction selection is already covered by the TableGen'erated code.

llvm-svn: 307904

Summary:
This patch replaces a bunch of iterator-based for loops with range-based
for loops. There are 2 iterator-based loops left in this file in
removeNotPreservedAnalysis, but I think those cannot be replaced by
range-based for loops as they modify the container they are iterating
over.

Unless I missed something, this schould be a NFC and I would appreciate
if someone could have a quick look to confirm that.

Reviewers: chandlerc, pcc, jhenderson

Reviewed By: jhenderson

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D35310

llvm-svn: 307902

[DAGCombiner] Fix issue with rotate combines asserting if the constant value types differ from the result type.

llvm-svn: 307900

This patch tidies up and organises ARM.td
so that it is easier to understandand
and extend in the future.

Reviewed by: @hahn, @rovka
Differential Revision: https://reviews.llvm.org/D35248

llvm-svn: 307897

Silence unused variable warning in release builds.
*sigh*

llvm-svn: 307896

llvm-svn: 307895

llvm-svn: 307894

Move a local variable from outside a switch to inside every case that
needs it (which isn't all of the cases, of course).

llvm-svn: 307893

llvm-svn: 307891

Should fix warnings in the build.

llvm-svn: 307890

Summary:
Similar to X86, it should be safe to inline callees if their
target-features are a subset of the caller. As some subtarget features
provide different instructions depending on whether they are set or
unset (e.g. ThumbMode and ModeSoftFloat), we use a whitelist of
target-features describing hardware capabilities only.

Reviewers: kristof.beyls, rengolin, t.p.northover, SjoerdMeijer, peter.smith, silviu.baranga, efriedma

Reviewed By: SjoerdMeijer, efriedma

Subscribers: dschuff, efriedma, aemerson, sdardis, javed.absar, arichardson, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D34697

llvm-svn: 307889

Patch by Carl Peto.

llvm-svn: 307888

llvm-svn: 307885

As far as I can tell we can simply distinguish based on features rather than model number. Many of the strings we were previously using are treated the same by the backend.

llvm-svn: 307884

Summary: Add TargetLowering hook getMMOFlags() to add target specific
MMO flags to load/store instructions created by ISel.

Reviewers: bogner, hfinkel, qcolombet, MatzeB

Subscribers: mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34962

llvm-svn: 307879

Summary: Add target hooks for printing and parsing target MMO flags.
Targets may override getSerializableMachineMemOperandTargetFlags() to
return a mapping from string to flag value for target MMO values that
should be serialized/parsed in MIR output.

Add implementation of this hook for AArch64 SuppressPair MMO flag.

Reviewers: bogner, hfinkel, qcolombet, MatzeB

Subscribers: mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34962

llvm-svn: 307877

llvm-svn: 307875

[libFuzzer] experimental feature -reduce_inputs (off by default) that tries to replace elements in the corpus with smaller ones that have the same feature set. Still needs tuning

llvm-svn: 307873

Code to convert MachO - specific section debug section names to standard DWARF v5
section names was in the wrong place.

Differential Revision: https://reviews.llvm.org/D35321

llvm-svn: 307872

When we fail to sink an instruction, we must make sure not to modify
the function; otherwise, we end up in an infinite loop because
CodeGenPrepare iterates until it doesn't make any changes.

Fixes https://bugs.llvm.org/show_bug.cgi?id=33608 .

llvm-svn: 307866

This is an incremental change to the promotion feature.

There are two problems with the current behavior:
1) loops with multiple exiting blocks are totally disabled
2) a counter update can only be promoted one level up in
  the loop nest -- which does help much for short trip
  count inner loops inside a high trip-count outer loops.

Due to this limitation, we still saw very large profile
count fluctuations from run to run for the affected loops
which are usually very hot.

This patch adds the support for promotion counters iteratively
across the loop nest. It also turns on the promotion for
loops with multiple exiting blocks (with a limit).

For single-threaded applications, the performance impact is flat
on average. For instance, dealII improves, but povray regresses.

llvm-svn: 307863

llvm-svn: 307862

Not all memory dependence queries succeed, so this needs to
be conservative if it fails.

llvm-svn: 307861

Summary:
Some programs run into a stack overflow issue. This change avoids this
problem by replacing the recursive algorithm with the iterative version.

Reviewers: MatzeB, t.p.northover, dblaikie

Reviewed By: MatzeB

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35105

llvm-svn: 307860

llvm-svn: 307858

llvm-svn: 307857

Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size.

Reviewers: eli.friedman, reames, mkazantsev, skatkov

Reviewed By: reames

Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits

Differential Revision: https://reviews.llvm.org/D34885

llvm-svn: 307854

Reviewers: evandro, t.p.northover, javed.absar

Reviewed By: evandro

Subscribers: aemerson, rengolin, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34959

llvm-svn: 307851

Summary: Different JITs and other clients of LLVM may have different needs in how symbol resolution should occur.

Reviewers: v.g.vassilev, lhames, karies

Reviewed By: v.g.vassilev

Subscribers: pcanal, llvm-commits

Differential Revision: https://reviews.llvm.org/D33529

llvm-svn: 307849