Commits · 44ee3efb931c639a8ca1017d7c251c2502887482 · Lorenzo Albano / LLVM bpEVL · GitLab

Jun 24, 2022
- [CodeGen] Simplify isVirtualRegister. NFC · 44ee3efb
  Fangrui Song authored Jun 23, 2022
  
  44ee3efb
- [AMDGPU][NFC] Correct typo in DWARF Extensions For Heterogeneous Debugging · 5d2cc4d8
  Venkata Ramanaiah Nalamothu authored Jun 20, 2022
  5d2cc4d8
- [GuardWidening] Update all tests with update_test_checks.py · 9ffe1b0a
  Serguei Katkov authored Jun 24, 2022
  
  9ffe1b0a
- [MachineSink] Clear kill flags on operands outside loop · 874fbe2c
  Carl Ritson authored Jun 24, 2022
  874fbe2c
- Revert "Add support for decoding base64." · f401dd6f
  Douglas Yung authored Jun 23, 2022
  f401dd6f
- [PowerPC][AIX] Fix assertion message on AIX. NFC. · 106657df
  Kai Luo authored Jun 24, 2022
  106657df
- [LegalizeTypes][NFC] Add an assert to WidenVecRes_EXTRACT_SUBVECTOR and adjust some code · 1ce30457
  Lian Wang authored Jun 17, 2022
  1ce30457
- [PowerPC] Allow llvm.ppc.cfence to accept pointer types · 6710b21d
  Kai Luo authored Jun 24, 2022
  6710b21d
- [SelectionDAG] Enable WidenVecOp_VECREDUCE for scalable vector · 770fe864
  Lian Wang authored Jun 21, 2022
  770fe864
- Add support for decoding base64. · 8b987ca5
  Greg Clayton authored May 23, 2022
  8b987ca5
- Revert "[LoopInterchange] New cost model for loop interchange" · 878309cc
  Evgenii Stepanov authored Jun 23, 2022
  878309cc
- [RISCV] Replace two calls to getMinRVVVectorSizeInBits with useRVVForFixedLengthVectors [nfc] · 7bfad7b9
  Philip Reames authored Jun 23, 2022
  
  7bfad7b9
Jun 23, 2022
- [WebAssembly][Object] Remove requirement that objects must have code sections · 5a082d9c
  Derek Schuff authored Jun 17, 2022
  5a082d9c
- [LoopInterchange] New cost model for loop interchange · 1b24fe34
  Congzhe Cao authored Jun 23, 2022
  1b24fe34
- [LV] Avoid a crash when costing a uniform store which doesn't correspond to a legal scatter · 46ea4b5e
  Philip Reames authored Jun 23, 2022
  46ea4b5e
- [ThinLTO][ELF] Add --thinlto-emit-index-files option · 22f12733
  Jin Xin Ng authored Jun 01, 2022
  22f12733
- [llvm] Update module map to include the `IR/ConstantFold` header · 148071fb
  Med Ismail Bennani authored Jun 23, 2022
  148071fb
- [SLP]Fix a crash when reorder masked gather nodes with reused scalars. · 3b6edef1
  Alexey Bataev authored Jun 22, 2022
  3b6edef1
- [Inline] Introduce a backend option to suppress inlining of functions with large stack sizes. · c50e6f59
  Wolfgang Pieb authored Jun 22, 2022
  c50e6f59
- [RISCV] Fix a crash in InsertVSETVLI where we hadn't properly guarded for a... · 1cc97922
  Philip Reames authored Jun 23, 2022
  1cc97922
- [ConstraintElimination] Use stable_sort to sort worklist. · d9526e8a
  Florian Hahn authored Jun 23, 2022
  d9526e8a
- [docs][NewPM] Add more info on why accessing mutable outer analyses is disallowed · 865812c3
  Arthur Eubanks authored Jun 22, 2022
  865812c3
- [test][GlobalOpt] Update precommitted test · b257acd2
  Arthur Eubanks authored Jun 23, 2022
  
  b257acd2
- [BasicTTI] Avoid crash when costing scalable select expansion · 0c132674
  Philip Reames authored Jun 23, 2022
  0c132674
- [gn build] Port 4045b62d · 57b0d940
  LLVM GN Syncbot authored Jun 23, 2022
  
  57b0d940
- [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f. · 8b10ffab
  Craig Topper authored Jun 23, 2022
  8b10ffab
- [RISCV] Add macrofusion infrastructure and one example usage. · 4045b62d
  Craig Topper authored Jun 23, 2022
  4045b62d
- [AMDGPU] gfx11 Select on Buffer Atomic FAdd Rtn type · ae72fee7
  Joe Nash authored Jun 20, 2022
  ae72fee7
- Revert "[ConstraintElimination] Transfer info from ULT to signed system." · 94ed2caf
  Florian Hahn authored Jun 23, 2022
  94ed2caf
- [ConstraintElimination] Transfer info from ULT to signed system. · 316e106f
  Florian Hahn authored Jun 23, 2022
  316e106f
- [AArch64][SVE] Match (add x (lsr/asr y c)) -> usra/ssra x y c · 6f27df50
  Bradley Smith authored Jun 17, 2022
  6f27df50
- [AMDGPU] Flush the vmcnt counter in loop preheaders when necessary · 79e77a9f
  Baptiste Saleil authored Jun 23, 2022
  79e77a9f
- Revert "[fastalloc] Support allocating specific register class in fastalloc" · 851a5efe
  Nico Weber authored Jun 23, 2022
  851a5efe
- [Binary] Fix leftoever line · 7c9a3825
  Joseph Huber authored Jun 23, 2022
  
  7c9a3825
- [Binary] Reserve the correct size for the OffloadBinary · 4e2a0092
  Joseph Huber authored Jun 23, 2022
  4e2a0092
- [BasicAA] Add test for call incorrectly treated as escape source (NFC) · 8b6f69a4
  Nikita Popov authored Jun 23, 2022
  
  8b6f69a4
- [ValueTracking] Teach isKnownNonZero that a vscale is never 0. · bd1a4c85
  David Green authored Jun 23, 2022
  bd1a4c85
- [LSR] Move transform test from test/Analysis to test/Transforms. · 9d2349c7
  Florian Hahn authored Jun 23, 2022
  9d2349c7
- [AMDGPU] Use -check-prefixes in a test. NFC. · 2b4931ef
  Jay Foad authored Jun 23, 2022
  
  2b4931ef
- [ConstraintElimination] Transfer info from SLT to unsigned system. · 9a33f397
  Florian Hahn authored Jun 23, 2022
  9a33f397