Commits · 505933a489206fc4b27f4fb4292c52097faa294e · Lorenzo Albano / LLVM bpEVL · GitLab

May 24, 2021
- [NVPTX] Fix lowering of frem for negative values · 505933a4
  thomasraoux authored May 24, 2021
  505933a4
- [CostModel][X86] Improve accuracy of vector non-uniform shift costs on XOP/AVX2 targets · 1ad4f887
  Simon Pilgrim authored May 24, 2021
  1ad4f887
- [AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND · e4051325
  Bradley Smith authored May 11, 2021
  e4051325
- [AArch64][SVE] Improve codegen for fixed length vector concat · 4bc14be2
  Bradley Smith authored May 14, 2021
  4bc14be2
- [ARM] Allow findLoopPreheader to return headers with multiple loop successors · 543406a6
  David Green authored May 24, 2021
  543406a6
- [ARM] Ensure WLS preheader blocks have branches during memcpy lowering · 53c42f77
  David Green authored May 24, 2021
  53c42f77
- [ARM] Fix inline memcpy trip count sequence · 6cc78b92
  David Green authored May 24, 2021
  6cc78b92
- [RISCV] Prevent store combining from infinitely looping · 7a211ed1
  Fraser Cormack authored May 21, 2021
  7a211ed1
- [CostModel][X86] Improve accuracy of vXi64 MUL costs on AVX2/AVX512 targets · 243e5886
  Simon Pilgrim authored May 23, 2021
  243e5886
- [AArch64] Delete unneeded fixup_aarch64_ldr_pcrel_imm19 VK_GOT special case · 249b40b5
  Fangrui Song authored May 23, 2021
  249b40b5
May 23, 2021
- [AArch64][MC] Remove unneeded "in .xxx directive" from diagnostics · fc82507c
  Fangrui Song authored May 23, 2021
  fc82507c
- [SPARC] recognize the "rd %pc, reg" special form · 30c413cd
  Joerg Sonnenberger authored May 23, 2021
  30c413cd
- [AArch64] Use \t in AsmStreamer to match the prevailing style · ff8be66c
  Fangrui Song authored May 23, 2021
  
  ff8be66c
- [CostModel][X86] Align v2i64 MUL costs on SSE42+ targets with worst case · e4ec5cc8
  Simon Pilgrim authored May 23, 2021
  e4ec5cc8
- [ARM] Add extra debug messages for gather/scatter lowering. NFC · edc2dca4
  David Green authored May 23, 2021
  
  edc2dca4
May 22, 2021
- [CostModel][X86] Align v4i64 MUL costs on AVX1 targets with worst case · fc01b9bd
  Simon Pilgrim authored May 22, 2021
  fc01b9bd
- [CostModel][X86] Pull out X86/X64 scalar int arithmetric costs from SSE tables. NFCI. · 6f9ac11e
  Simon Pilgrim authored May 21, 2021
  6f9ac11e
- [CostModel][X86] vXi8 MUL is always promoted to vXi16 · 7a898477
  Simon Pilgrim authored May 22, 2021
  
  7a898477
- [CostModel][X86] Improve v8i32 MUL costs on AVX1 targets to account for slower btver2 · 9bd0dc83
  Simon Pilgrim authored May 22, 2021
  9bd0dc83
- Reland [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost() · 8ed0864f
  Roman Lebedev authored May 22, 2021
  8ed0864f
- Reland [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again · 05a4e4a8
  Roman Lebedev authored May 22, 2021
  05a4e4a8
- [IR] make stack-protector-guard-* flags into module attrs · 033138ea
  Nick Desaulniers authored May 21, 2021
  033138ea
May 21, 2021
- RISCV: add a few deprecated aliases for CSRs · 6c6b3e3a
  Saleem Abdulrasool authored May 05, 2021
  6c6b3e3a
- [CostModel][X86] Improve f64/v2f64/v4f64 FMUL costs on AVX1 targets to account for slower btver2 · fe6c11c5
  Simon Pilgrim authored May 21, 2021
  fe6c11c5
- [X86] Inline variable to avoid unused warning in Release builds. NFCI. · ea438b48
  Benjamin Kramer authored May 21, 2021
  
  ea438b48
- [CostModel][X86] Improve fneg costs · 2fca5558
  Simon Pilgrim authored May 21, 2021
  2fca5558
- [X86] Lower calls with clang.arc.attachedcall bundle · c2d44bd2
  Florian Hahn authored May 21, 2021
  c2d44bd2
- [X86] Don't fold (fneg (fma (fneg X), Y, (fneg Z))) to (fma X, Y, Z) · 44568059
  Jim Lin authored May 21, 2021
  44568059
- [TTI] NFC: Change getCostOfKeepingLiveOverCall to return InstructionCost. · e1cb98be
  Daniil Fukalov authored May 20, 2021
  e1cb98be
- [CostModel][X86] Tweak fptoui v4f32->v4i32 + v8f32->v8i32 SSE/AVX costs · 3ae7f7ae
  Simon Pilgrim authored May 21, 2021
  3ae7f7ae
- [CostModel][X86] Match SSE41 legalized conversion costs as well as SSE2 · 4865ed30
  Simon Pilgrim authored May 21, 2021
  
  4865ed30
- [CostModel][X86] Add uitpfp v4f32->v4i32 + v8f32->v8i32 SSE/AVX costs · eb6429d0
  Simon Pilgrim authored May 21, 2021
  eb6429d0
- Fix warning: comparison of integer expressions of different signedness. NFC · e2815398
  Luke Benes authored May 21, 2021
  e2815398
- [ARM] Fix the operand used for WLS in ARMLowOverheadLoops · e7a6df68
  David Green authored May 21, 2021
  e7a6df68
- [AMDGPU] Request module used variables from LDS lowering as internal · 49028858
  Stanislav Mekhanoshin authored May 20, 2021
  49028858
- [AMDGPU] Fix module LDS selection · 748db5bf
  Stanislav Mekhanoshin authored May 20, 2021
  748db5bf
May 20, 2021
- [M68k] Support for inline asm operands w/ simple constraints · dccf5c7d
  Min-Yih Hsu authored May 06, 2021
  dccf5c7d
- [M68k] Allow user to preserve certain registers · e620bea2
  Min-Yih Hsu authored May 16, 2021
  e620bea2
- [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach... · e10958c8
  Jessica Clarke authored May 20, 2021
  e10958c8
- [RISCV] Ensure small mask BUILD_VECTORs aren't expanded · c74ab891
  Fraser Cormack authored May 19, 2021
  c74ab891