Use new vector insert half-word and byte instructions when we see insertelement on '8 x i16' and '16 x i8' types.  Also extended existing lit testcase to cover these cases.

Differential Revision: https://reviews.llvm.org/D34630

llvm-svn: 317613

llvm-svn: 317612

This patch teaches the test suite configuration about the -std=c++2a
flag. And, since it's the newest dialect, change the test suite to
choose it, if possible, by default.

llvm-svn: 317611

This patch changes the test suite to attempt and prefer -std=c++17 over
-std=c++1z. It also fixes the REQUIRES and UNSUPPORTED lit markers
to refer to c++17 over c++1z.

llvm-svn: 317610

llvm-svn: 317609

Summary:
When testing a merge of compiler-rt r304709 into gcc trunk on x86-64-pc-linux-gnu,
I ran into two compile errors:
sanitizer_common/sanitizer_symbolizer_libbacktrace.cc:96:73: error: no matching function for call to '__sanitizer::AddressInfo::FillModuleInfo(char*&, __sanitizer::uptr&)'

All other files in sanitizer_common (with the exception of sanitizer_malloc_mac.inc
which is special) include sanitizer_platform.h without directory name.

Patch by Mike Jongen

Reviewers: kcc, vitalybuka

Reviewed By: kcc

Subscribers: kubamracek, fedor.sergeev, llvm-commits

Differential Revision: https://reviews.llvm.org/D33933

llvm-svn: 317608

Supporting this form in .debug_line.dwo will be done as a follow-up.

Differential Revision: https://reviews.llvm.org/D33155

llvm-svn: 317607

Differential Revision: https://reviews.llvm.org/D39079

llvm-svn: 317605

Summary: This change allows Fuchsia to boot properly using the Scudo allocator.

Reviewers: cryptoad, alekseyshl, krytarowski

Reviewed By: cryptoad, krytarowski

Subscribers: krytarowski, kubamracek, llvm-commits

Differential Revision: https://reviews.llvm.org/D39490

llvm-svn: 317604

Differential Revision: https://reviews.llvm.org/D39748

llvm-svn: 317601

The hexagon test should be fixed now.

Original commit message:

This pulls shifts through a select+binop with a constant where the select conditionally executes the binop. We already do this for just the binop, but not with the select.

This can allow us to get the select closer to other selects to enable removing one.

Differential Revision: https://reviews.llvm.org/D39222

llvm-svn: 317600

rdar://33875453

llvm-svn: 317599

This patch renames some of the flag names of the clang/libomptarget map interface. The old names are slightly misleading, whereas the new ones describe in a better way what each flag is about.

Only the macros within the enumeration are renamed, there is no change in functionality therefore there are no updated regression tests.

Differential Revision: https://reviews.llvm.org/D39745

llvm-svn: 317598

The starting location is the location of the '.'

llvm-svn: 317596

Datalayout is no longer optional so the comment didn't match what the code currently does.

llvm-svn: 317594

rdar://35109556

llvm-svn: 317593

An "or" that sets the sign-bit can be replaced with a "xor", if
the sign-bit was known to be clear before. With some changes to
instruction combining, the simple sign-bit check was failing.
Replace it with a more flexible one to catch more cases.

llvm-svn: 317592

Patch [5/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39091

llvm-svn: 317591

Patch [3/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

To summarise, this patch adds:

 * SVE register definitions
 * Methods to parse SVE register operands
 * Methods to print SVE register operands
 * RegKind SVEDataVector to distinguish it from other data types like scalar register or Neon vector.
 * k_SVEDataRegister and SVEDataRegOp to describe SVE registers (which will be extended by further patches with e.g. ElementWidth and the shift-extend type).


Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39089

llvm-svn: 317590

Return false for swifterror support until the backend is fixed.

llvm-svn: 317589

llvm-svn: 317588

We allow usage of global/per-thread data with non-trivial ctors/dtors
throughout tsan code base by placing all global/per-thread data into
Context/ThreadState and then explicitly constructing them with
placement new. This greatly simplifies code by restricting the
"linker initialized plague" to only these 2 objects.

Do the same for interceptors data.

This allows to use Vector instead of bunch of hand-written code in:
https://reviews.llvm.org/D39619

Reviewed in: https://reviews.llvm.org/D39721

llvm-svn: 317587

Summary:
Update sanitizer_allocator to use new API.
    
Second patch in a series.  First patch https://reviews.llvm.org/D39072
    
Updates MmapNoAccess / MmapFixed call sites in the saniziter_allocator
to use the new Init/Map APIs instead.


Reviewers: alekseyshl, cryptoad, phosek, mcgrathr, dvyukov

Reviewed By: alekseyshl, cryptoad

Subscribers: dvyukov, mcgrathr, kubamracek

Differential Revision: https://reviews.llvm.org/D38592

llvm-svn: 317586

Summary:
When an inclusion is not processed as part of the preamble, its path is
not made into an absolute path as part of the precompiled header code
(adjustFilenameForRelocatableAST in ASTWriter.cpp). Because of this,
when we convert a Decl location to retrieve the file name with
FileEntry->getName(), it is possible for this path to be relative.
Instead, we should try to use tryGetRealPathName first which returns
an absolute path.

Fixes bug 35217.

Reviewers: sammccall, ilya-biryukov, rwols, Nebiroth

Reviewed By: sammccall

Subscribers: cfe-commits, ilya-biryukov

Tags: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D39705

llvm-svn: 317585

llvm-svn: 317584

The files are already large, and we may need to add even more RUNs to 
distinguish differences based on OS, environment, or other platform things.

llvm-svn: 317583

Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39090

llvm-svn: 317582

llvm-svn: 317581

llvm-svn: 317580

Reland r317100 with minor fix regarding ComputeCommonTailLength function in
BranchFolding.cpp. Skipping top CFI instructions block needs to executed on
several more return points in ComputeCommonTailLength().

Original r317100 message:

"Correct dwarf unwind information in function epilogue for X86"

This patch aims to provide correct dwarf unwind information in function
epilogue for X86.

It consists of two parts. The first part inserts CFI instructions that set
appropriate cfa offset and cfa register in emitEpilogue() in
X86FrameLowering. This part is X86 specific.

The second part is platform independent and ensures that:

- CFI instructions do not affect code generation
- Unwind information remains correct when a function is modified by
  different passes. This is done in a late pass by analyzing information
  about cfa offset and cfa register in BBs and inserting additional CFI
  directives where necessary.

Changed CFI instructions so that they:

- are duplicable
- are not counted as instructions when tail duplicating or tail merging
- can be compared as equal

Added CFIInstrInserter pass:

- analyzes each basic block to determine cfa offset and register valid at
  its entry and exit
- verifies that outgoing cfa offset and register of predecessor blocks match
  incoming values of their successors
- inserts additional CFI directives at basic block beginning to correct the
  rule for calculating CFA

Having CFI instructions in function epilogue can cause incorrect CFA
calculation rule for some basic blocks. This can happen if, due to basic
block reordering, or the existence of multiple epilogue blocks, some of the
blocks have wrong cfa offset and register values set by the epilogue block
above them.

CFIInstrInserter is currently run only on X86, but can be used by any target
that implements support for adding CFI instructions in epilogue.

Patch by Violeta Vukobrat.

llvm-svn: 317579

Reported by http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/6000/steps/build-unified-tree/logs/stdio
The error messages were all similar to:
llvm\unittests\CodeGen\GlobalISel\LegalizerInfoTest.cpp(54): error C2398: Element '1': conversion from '' to 'unsigned int' requires a narrowing conversion

llvm-svn: 317578

Summary: This is a refactoring change. NFC

Reviewers: arphaman, hokein

Reviewed By: arphaman, hokein

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D39675

llvm-svn: 317577

Summary:
The cost calculation for default case on X86 target does not always
follow correct wayt because of missing 4-th argument in
`BaseT::getCastInstrCost()` call. Added this missing parameter.

Reviewers: hfinkel, mkuper, RKSimon, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39687

llvm-svn: 317576

llvm-svn: 317575

llvm-svn: 317574

... to silence gcc 7's default -Wimplicit-fallthrough.

llvm-svn: 317573

Summary:
This makes it very easy to test files that only differ in a constant
value somewhere in the test case.

Reviewers: jlebar, hfinkel, chandlerc, probinson

Reviewed By: probinson

Subscribers: probinson, llvm-commits

Differential Revision: https://reviews.llvm.org/D39629

llvm-svn: 317572

llvm-svn: 317571

Redundant Expression Checker is updated to be able to detect expressions that
contain macros. Also, other small details are modified to improve the current
implementation.

The improvements in detail are as follows:
* Binary and ternary operator expressions containing two constants, with at
least one of them from a macro, are detected and tested for redundancy.

Macro expressions are treated somewhat differently from other expressions,
because the particular values of macros can vary across builds.
They can be considered correct and intentional, even if macro values equal,
produce ranges that exclude each other or fully overlap, etc. 

* The code structure is slightly modified: typos are corrected,
comments are added and some functions are renamed to improve comprehensibility,
both in the checker and the test file. A few test cases are moved to another
function.

* The checker is now able to detect redundant CXXFunctionalCastExprs as well.
A corresponding test case is added.

Patch by: Lilla Barancsuk!

Differential Revision: https://reviews.llvm.org/D38688

llvm-svn: 317570

Patch [2/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

This change is a non functional change that adds RegKind as an alternative to 'isVector' to prepare it for newer types (SVE data vectors and predicate vectors) that will be added in next patches (where the SVE data vector is added as part of this patch set)

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39088

llvm-svn: 317569