Commits · 84aa58cbe21696e2bbe56d50f045f44a7799171a · Lorenzo Albano / LLVM bpEVL · GitLab

Apr 08, 2020
- CodeGen: Use Register in TargetLowering · 84aa58cb
  Matt Arsenault authored Apr 08, 2020
  
  84aa58cb
- [PowerPC][AIX] Enable passing byval formal arguments in multiple registers. · 8abfd2c3
  Sean Fertile authored Mar 24, 2020
  8abfd2c3
- [PowerPC][Future] Add Support For Functions That Do Not Use A TOC. · 6c4b40de
  Stefan Pintilie authored Apr 08, 2020
  6c4b40de
- [X86][SSE] Combine PTEST(AND(X,Y),AND(X,Y)) -> PTEST(X,Y) and ANDN equivalents · 66c18c72
  Simon Pilgrim authored Apr 08, 2020
  66c18c72
- [X86][MC] Support enhanced relaxation for branch align · 916044d8
  Shengchen Kan authored Apr 07, 2020
  916044d8
- [ARM][MVE] Optimise offset addresses of gathers/scatters · 89e1248d
  Anna Welker authored Apr 08, 2020
  89e1248d
- [VE] Simplify definitions of uimm6 and simm7 · aa034867
  Kazushi (Jam) Marukawa authored Apr 08, 2020
  aa034867
- [AMDGPU] Expand vector trunc stores from i16 to i8 · f96810ff
  Stanislav Mekhanoshin authored Apr 07, 2020
  f96810ff
- [NFC] Clean up uses of LoadInst constructor. · 565b56a7
  Eli Friedman authored Apr 07, 2020
  
  565b56a7
- [VE] Migrate to the getMachineMemOperand overload using llvm::Align · 624654fd
  Fangrui Song authored Apr 07, 2020
  624654fd
- CodeGen: More conversions to use Register · 6011627f
  Matt Arsenault authored Apr 07, 2020
  
  6011627f
- [VE] Adapt aa26dd98 and 2481f26a · 2f8fb4d1
  Fangrui Song authored Apr 07, 2020
  
  2f8fb4d1
Apr 07, 2020
- [AMDGPU] Implement copyPhysReg for 16 bit subregs · 96e51ed0
  Stanislav Mekhanoshin authored Feb 28, 2020
  96e51ed0
- CodeGen: Use Register in TargetFrameLowering · 2481f26a
  Matt Arsenault authored Apr 07, 2020
  
  2481f26a
- CodeGen: Use Register in more places · aa26dd98
  Matt Arsenault authored Apr 07, 2020
  
  aa26dd98
- [NFC][PowerPC] Fix register class for patterns using XXPERMDIs · ecd84354
  Nemanja Ivanovic authored Apr 07, 2020
  ecd84354
- [AMDGPU] Extend constant folding for logical operations · a19a56f6
  Graham Sellers authored Apr 07, 2020
  a19a56f6
- [SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector. · c41685b1
  Craig Topper authored Apr 07, 2020
  c41685b1
- [AArch64] Don't expand memcmp in strict align mode. · e9ac757f
  Eli Friedman authored Apr 06, 2020
  e9ac757f
- AMDGPU: Use early return · f596ab40
  Matt Arsenault authored Apr 07, 2020
  
  f596ab40
- [WebAssembly][MC] Fix leak of std::string members in MCSymbolWasm · 5be42f36
  Sam Clegg authored Apr 06, 2020
  5be42f36
- [AMDGPU] Limit endcf-collapase to simple if · 12a32439
  Stanislav Mekhanoshin authored Apr 06, 2020
  12a32439
- [NFC][PowerPC] Cleanup 64-bit and Darwin CalleeSavedRegs · b9245f14
  David Tenty authored Apr 07, 2020
  b9245f14
- [X86][SSE] combineX86ShufflesConstants - early out for zeroable vectors (PR45443) · e3b60597
  Simon Pilgrim authored Apr 07, 2020
  e3b60597
- [ARM] unwinding .pad instructions missing in execute-only prologue · 01dc1077
  Keith Walker authored Mar 26, 2020
  01dc1077
- [ARM] Remove condition that could never be true · 14c1e987
  Peter Smith authored Apr 01, 2020
  14c1e987
- [WebAssembly] EmscriptenEHSjLj: Mark more functions as imported · f0bbf3d0
  Sam Clegg authored Apr 02, 2020
  f0bbf3d0
- Enable IBT(Indirect Branch Tracking) in JIT with CET(Control-flow Enforcement Technology) · 01a32f2b
  Xiang1 Zhang authored Apr 07, 2020
  01a32f2b
- Remove SequentialType from the type heirarchy. · 68b03aee
  Eli Friedman authored Apr 06, 2020
  68b03aee
Apr 06, 2020
- X86ISelLowering: Minor refactor to avoid redundant initialization while... · 5aead592
  David Blaikie authored Apr 06, 2020
  5aead592
- [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. · 72e87549
  Konstantin Pyzhov authored Apr 06, 2020
  72e87549
- AMDGPU: Remove dead paths for requiresUniformRegister · 869f05c8
  Matt Arsenault authored Feb 06, 2020
  869f05c8
- Revert e1730cfe · 51dc0283
  Konstantin Pyzhov authored Apr 06, 2020
  
  51dc0283
- [AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU. · e1730cfe
  Konstantin Pyzhov authored Apr 06, 2020
  e1730cfe
- [AArch64] Allow logical immediates to have all-1 in top bits · a5d375e0
  Fangrui Song authored Mar 09, 2020
  a5d375e0
- AMDGPU/GlobalISel: Select llvm.amdgcn.div.scale · 8a5f0daf
  Matt Arsenault authored Apr 05, 2020
  
  8a5f0daf
- AMDGPU/GlobalISel: Fix llvm.amdgcn.div.fmas.ll · e87ec667
  Matt Arsenault authored Apr 05, 2020
  
  e87ec667
- [AMDGPU] Fix inaccurate comments · ddd2f4b9
  Jay Foad authored Apr 06, 2020
  
  ddd2f4b9
- [AIX][PPC] Implement by-val caller arguments in multiple registers · d6ea82d1
  Chris Bowler authored Apr 06, 2020
  d6ea82d1
- AMDGPU: Use DAG patterns for div_fmas · cbf719b5
  Matt Arsenault authored Dec 20, 2019
  
  cbf719b5