- Jun 10, 2016
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Simon Pilgrim authored
llvm-svn: 272319
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- Jun 09, 2016
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Quentin Colombet authored
When we delete a live-range, we check if that live-range is the origin of others to keep it around for rematerialization. For that we check that the instruction we are about to remove is the same as the definition of the VNI of the original live-range. If this is the case, we just shrink the live-range to an empty one. Now, when we try to delete one of the children of such live-range (product of splitting), we do the same check. However, now the original live-range is empty and there is no way we can access the VNI to check its definition, and we crash. When we cannot get the VNI for the original live-range, that means we are not in the presence of the original definition. Thus, this check does not need to happen in that case and the crash is sloved! This bug was introduced in r266162 | wmi | 2016-04-12 20:08:27. It affects every target that uses the greedy register allocator. To happen, we need to delete both a the original instruction and its split products, in that order. This is likely to happen when rematerialization comes into play. Trying to produce a more robust test case. Will follow in a coming commit. This fixes llvm.org/PR27983. rdar://problem/26651519 llvm-svn: 272314
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Vedant Kumar authored
llvm-svn: 272309
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Simon Pilgrim authored
Auto-upgrade to generic shuffles like sse/avx2 implementations now that we can lower to VPSLLDQ/VPSRLDQ llvm-svn: 272308
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Simon Pilgrim authored
llvm-svn: 272307
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Duncan P. N. Exon Smith authored
r267296 used std::piecewise_construct without using std::forward_as_tuple, and r267298 hacked it out (using an emplace_back followed by a couple of reset() calls) because of a problem on a bot. I'm finally circling back to call forward_as_tuple as I should have to begin with (thanks to David Blaikie for pointing out the missing piece). Note that this code uses emplace_back() instead of push_back(make_pair()) because the move constructor for TrackingMDRef is expensive (cheaper than a copy, but still expensive). llvm-svn: 272306
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Simon Pilgrim authored
512-bit VPSLLDQ/VPSRLDQ can only be used for avx512bw targets so lowerVectorShuffleAsShift had to be adjusted to include the subtarget llvm-svn: 272300
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Justin Lebar authored
Summary: Currently clang emits these instructions via inline (volatile) asm in the CUDA headers. Switching to intrinsics will let the optimizer reason across calls to these intrinsics. Reviewers: tra Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D21160 llvm-svn: 272298
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Sanjoy Das authored
- Alphabetically sort the initializeXXX calls (this was brought up in D21115) - Remove repeated function names from doxygen comments llvm-svn: 272297
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Justin Lebar authored
Summary: __syncthreads, which corresponds to bar.sync 0, is already convergent. This makes the more general bar.sync n likewise convergent. Reviewers: tra Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D21161 llvm-svn: 272295
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Easwaran Raman authored
Differential Revision: http://reviews.llvm.org/D21090 llvm-svn: 272294
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Vedant Kumar authored
This reverts commit r272290. It breaks a test that depends on being able to seek the /dev/null equivalent on Windows: http://bb.pgr.jp/builders/ninja-clang-x64-mingw64-RA/builds/11360 llvm-svn: 272293
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Wei Ding authored
We were using the fast fdiv lowering for all division, implementation of IEEE754 fdiv is added. http://reviews.llvm.org/D20557 llvm-svn: 272292
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Vedant Kumar authored
Use os.devnull instead of tempfiles when substituting '/dev/null' on Windows machines. This should make the bots just a bit speedier. Thanks to Yunzhong Gao for testing this patch on Windows! Differential Revision: http://reviews.llvm.org/D20549 llvm-svn: 272290
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Michael Kuperstein authored
Previously, we materialized secondary vector IVs from the primary scalar IV, by offseting the primary to match the correct start value, and then broadcasting it - inside the loop body. Instead, we can use a real vector IV, like we do for the primary. This enables using vector IVs for secondary integer IVs whose type matches the type of the primary. Differential Revision: http://reviews.llvm.org/D20932 llvm-svn: 272283
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Chris Bieneman authored
This is the more-correct fix to out-of-tree building. AddLLVM.cmake relies on this variable being set, so we should make sure it is set in LLVMConfig.cmake. llvm-svn: 272279
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Davide Italiano authored
llvm-svn: 272278
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Davide Italiano authored
Thanks to Rafael for the suggestion. llvm-svn: 272277
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Jan Vesely authored
Fixes {u,}long_{min,max,clamp} opencl piglit regressions on EG. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D17898 llvm-svn: 272272
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Hans Wennborg authored
llvm-svn: 272269
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Haicheng Wu authored
This reapplies commit r271930, r271915, r271923. They hit a bug in Thumb which is fixed in r272258 now. The original message: The code layout that TailMerging (inside BranchFolding) works on is not the final layout optimized based on the branch probability. Generally, after BlockPlacement, many new merging opportunities emerge. This patch calls Tail Merging after MBP and calls MBP again if Tail Merging merges anything. llvm-svn: 272267
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Ulrich Weigand authored
This enables use of the 'S' constraint for inline ASM operands on SystemZ, which allows for a memory reference with a signed 20-bit immediate displacement. This patch includes corresponding documentation and test case updates. I've changed the 'T' constraint to match the new behavior for 'S', as 'T' also uses a long displacement (though index constraints are still not implemented). I also changed 'm' to match the behavior for 'S' as this will allow for a wider range of displacements for 'm', though correct me if that's not the right decision. Author: colpell Differential Revision: http://reviews.llvm.org/D21097 llvm-svn: 272266
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Davide Italiano authored
llvm-svn: 272264
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Davide Italiano authored
Fixes a crash in the backend during an LTO build of rtld(1) in FreeBSD. llvm-svn: 272262
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Hrvoje Varga authored
Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
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James Molloy authored
ReplaceTailWithBranchTo assumed that if an instruction is predicated, it must be part of an IT block. This is not correct for conditional branches. No testcase as this was triggered by the reverted patch r272017 - test coverage will occur when that patch is re-reverted and there is no known way to trigger this in the meantime. llvm-svn: 272258
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Igor Breger authored
This is complement patch to D21060. Differential Revision: http://reviews.llvm.org/D21174 llvm-svn: 272257
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Zlatko Buljan authored
[mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, SELNEZ.* and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D20862 llvm-svn: 272256
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Sam Kolton authored
Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21129 llvm-svn: 272255
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Diana Picus authored
This is made possible by removing an assert in llc that assumed MIRParser::parseLLVMModule would exit on error. MIRParser's documentation states that it returns null if a parsing error occurs, so there's no reason to assert. We can instead just fall through to where the check for a module is performed and exit if it is null. This commit is part of the clean-up after r269655. Fixes PR27770 Differential Revision: http://reviews.llvm.org/D20371 llvm-svn: 272254
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Craig Topper authored
[AVX512] Fix shuffle decode printing for several instructions with write masks. There are still more bugs here with UNPCK and PALIGN for sure. But these were the easiest ones to fix. llvm-svn: 272252
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James Molloy authored
If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 272251
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Craig Topper authored
llvm-svn: 272250
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Craig Topper authored
[X86] Bring consistent naming to the SSE/AVX and AVX512 PALIGNR instructions. Then add shuffle decode printing for the EVEX forms which is made easier by having the naming structure more similar to other instructions. llvm-svn: 272249
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Craig Topper authored
llvm-svn: 272248
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Xinliang David Li authored
llvm-svn: 272243
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Saleem Abdulrasool authored
llvm-svn: 272242
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Saleem Abdulrasool authored
Add support to the AArch64 IAS for the `.arch` directive. This allows the assembly input to use architectural functionality in part of a file. This is used in existing code like BoringSSL. Resolves PR26016! llvm-svn: 272241
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Kostya Serebryany authored
llvm-svn: 272240
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Teresa Johnson authored
Summary: Enable existing summary-based importing support in the gold-plugin. Reviewers: mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: http://reviews.llvm.org/D21080 llvm-svn: 272239
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